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https://github.com/AsahiLinux/u-boot
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clk: zynqmp: Add clock driver support for zynqmp
Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Siva Durga Prasad Paladugu
Michal Simek
parent
5ce987feb3
commit
128ec1fe6f
3 changed files with 249 additions and 0 deletions
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@ -28,6 +28,13 @@ config CLK_BOSTON
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help
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Enable this to support the clocks
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config CLK_ZYNQMP
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bool "Enable clock driver support for ZynqMP"
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depends on ARCH_ZYNQMP
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help
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This clock driver adds support for clock realted settings for
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ZynqMP platform.
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source "drivers/clk/tegra/Kconfig"
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source "drivers/clk/uniphier/Kconfig"
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source "drivers/clk/exynos/Kconfig"
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@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o
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obj-y += tegra/
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obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
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241
drivers/clk/clk_zynqmp.c
Normal file
241
drivers/clk/clk_zynqmp.c
Normal file
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@ -0,0 +1,241 @@
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/*
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* ZynqMP clock driver
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*
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* Copyright (C) 2016 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <clk.h>
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#define ZYNQMP_GEM0_REF_CTRL 0xFF5E0050
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#define ZYNQMP_IOPLL_CTRL 0xFF5E0020
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#define ZYNQMP_RPLL_CTRL 0xFF5E0030
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#define ZYNQMP_DPLL_CTRL 0xFD1A002C
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#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
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#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
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#define ZYNQMP_SIP_SVC_MMIO_WRITE 0xC2000013
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#define ZYNQMP_SIP_SVC_MMIO_READ 0xC2000014
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#define ZYNQMP_DIV_MAX_VAL 0x3F
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#define ZYNQMP_DIV1_SHFT 8
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#define ZYNQMP_DIV1_SHFT 8
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#define ZYNQMP_DIV2_SHFT 16
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#define ZYNQMP_DIV_MASK 0x3F
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#define ZYNQMP_PLL_CTRL_FBDIV_MASK 0x7F
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#define ZYNQMP_PLL_CTRL_FBDIV_SHFT 8
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#define ZYNQMP_GEM_REF_CTRL_SRC_MASK 0x7
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#define ZYNQMP_GEM0_CLK_ID 45
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#define ZYNQMP_GEM1_CLK_ID 46
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#define ZYNQMP_GEM2_CLK_ID 47
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#define ZYNQMP_GEM3_CLK_ID 48
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static unsigned long pss_ref_clk;
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static int zynqmp_calculate_divisors(unsigned long req_rate,
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unsigned long parent_rate,
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u32 *div1, u32 *div2)
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{
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u32 req_div = 1;
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u32 i;
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/*
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* calculate two divisors to get
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* required rate and each divisor
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* should be less than 63
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*/
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req_div = DIV_ROUND_UP(parent_rate, req_rate);
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for (i = 1; i <= req_div; i++) {
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if ((req_div % i) == 0) {
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*div1 = req_div / i;
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*div2 = i;
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if ((*div1 < ZYNQMP_DIV_MAX_VAL) &&
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(*div2 < ZYNQMP_DIV_MAX_VAL))
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return 0;
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}
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}
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return -1;
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}
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static int zynqmp_get_periph_id(unsigned long id)
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{
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int periph_id;
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switch (id) {
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case ZYNQMP_GEM0_CLK_ID:
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periph_id = 0;
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break;
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case ZYNQMP_GEM1_CLK_ID:
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periph_id = 1;
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break;
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case ZYNQMP_GEM2_CLK_ID:
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periph_id = 2;
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break;
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case ZYNQMP_GEM3_CLK_ID:
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periph_id = 3;
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break;
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default:
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printf("%s, Invalid clock id:%ld\n", __func__, id);
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return -EINVAL;
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}
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return periph_id;
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}
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static int zynqmp_set_clk(unsigned long id, u32 div1, u32 div2)
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{
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struct pt_regs regs;
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ulong reg;
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u32 mask, value;
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id = zynqmp_get_periph_id(id);
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if (id < 0)
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return -EINVAL;
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reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id);
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mask = (ZYNQMP_DIV_MASK << ZYNQMP_DIV1_SHFT) |
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(ZYNQMP_DIV_MASK << ZYNQMP_DIV2_SHFT);
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value = (div1 << ZYNQMP_DIV1_SHFT) | (div2 << ZYNQMP_DIV2_SHFT);
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debug("%s: reg:0x%lx, mask:0x%x, value:0x%x\n", __func__, reg, mask,
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value);
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regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_WRITE;
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regs.regs[1] = ((u64)mask << 32) | reg;
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regs.regs[2] = value;
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regs.regs[3] = 0;
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smc_call(®s);
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return regs.regs[0];
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}
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static unsigned long zynqmp_clk_get_rate(struct clk *clk)
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{
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struct pt_regs regs;
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ulong reg;
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unsigned long value;
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int id;
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id = zynqmp_get_periph_id(clk->id);
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if (id < 0)
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return -EINVAL;
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reg = (ulong)((u32 *)ZYNQMP_GEM0_REF_CTRL + id);
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regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ;
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regs.regs[1] = reg;
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regs.regs[2] = 0;
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regs.regs[3] = 0;
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smc_call(®s);
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value = upper_32_bits(regs.regs[0]);
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value &= ZYNQMP_GEM_REF_CTRL_SRC_MASK;
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switch (value) {
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case 0:
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regs.regs[1] = ZYNQMP_IOPLL_CTRL;
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break;
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case 2:
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regs.regs[1] = ZYNQMP_RPLL_CTRL;
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break;
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case 3:
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regs.regs[1] = ZYNQMP_DPLL_CTRL;
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break;
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default:
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return -EINVAL;
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}
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regs.regs[0] = ZYNQMP_SIP_SVC_MMIO_READ;
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regs.regs[2] = 0;
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regs.regs[3] = 0;
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smc_call(®s);
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value = upper_32_bits(regs.regs[0]) &
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(ZYNQMP_PLL_CTRL_FBDIV_MASK <<
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ZYNQMP_PLL_CTRL_FBDIV_SHFT);
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value >>= ZYNQMP_PLL_CTRL_FBDIV_SHFT;
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value *= pss_ref_clk;
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return value;
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}
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static ulong zynqmp_clk_set_rate(struct clk *clk, unsigned long clk_rate)
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{
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int ret;
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u32 div1 = 0;
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u32 div2 = 0;
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unsigned long input_clk;
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input_clk = zynqmp_clk_get_rate(clk);
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if (IS_ERR_VALUE(input_clk)) {
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dev_err(dev, "failed to get input_clk\n");
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return -EINVAL;
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}
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debug("%s: i/p CLK %ld, clk_rate:0x%ld\n", __func__, input_clk,
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clk_rate);
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ret = zynqmp_calculate_divisors(clk_rate, input_clk, &div1, &div2);
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if (ret) {
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dev_err(dev, "failed to proper divisors\n");
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return -EINVAL;
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}
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debug("%s: Div1:%d, Div2:%d\n", __func__, div1, div2);
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ret = zynqmp_set_clk(clk->id, div1, div2);
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if (ret) {
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dev_err(dev, "failed to set gem clk\n");
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return -EINVAL;
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}
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return 0;
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}
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static int zynqmp_clk_probe(struct udevice *dev)
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{
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struct clk clk;
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int ret;
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debug("%s\n", __func__);
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ret = clk_get_by_name(dev, "pss_ref_clk", &clk);
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if (ret < 0) {
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dev_err(dev, "failed to get pss_ref_clk\n");
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return ret;
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}
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pss_ref_clk = clk_get_rate(&clk);
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if (IS_ERR_VALUE(pss_ref_clk)) {
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dev_err(dev, "failed to get rate pss_ref_clk\n");
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return -EINVAL;
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}
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return 0;
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}
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static struct clk_ops zynqmp_clk_ops = {
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.set_rate = zynqmp_clk_set_rate,
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.get_rate = zynqmp_clk_get_rate,
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};
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static const struct udevice_id zynqmp_clk_ids[] = {
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{ .compatible = "xlnx,zynqmp-clkc" },
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{ }
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};
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U_BOOT_DRIVER(zynqmp_clk) = {
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.name = "zynqmp-clk",
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.id = UCLASS_CLK,
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.of_match = zynqmp_clk_ids,
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.probe = zynqmp_clk_probe,
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.ops = &zynqmp_clk_ops,
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};
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