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u-boot/arch/arm/mach-tegra/tegra30/clock.c

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Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/*
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-25 16:50:44 +00:00
* (C) Copyright 2010-2015
* NVIDIA Corporation <www.nvidia.com>
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
*
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-25 16:50:44 +00:00
* SPDX-License-Identifier: GPL-2.0+
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
*/
/* Tegra30 Clock control functions */
#include <common.h>
ARM: tegra: Implement tegra_plle_enable() This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-10 05:25:06 +00:00
#include <errno.h>
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>
/*
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
* Clock types that we can use as a source. The Tegra30 has muxes for the
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
* peripheral clocks, and in most cases there are four options for the clock
* source. This gives us a clock 'type' and exploits what commonality exists
* in the device.
*
* Letters are obvious, except for T which means CLK_M, and S which means the
* clock derived from 32KHz. Beware that CLK_M (also called OSC in the
* datasheet) and PLL_M are different things. The former is the basic
* clock supplied to the SOC from an external oscillator. The latter is the
* memory clock PLL.
*
* See definitions in clock_id in the header file.
*/
enum clock_type_id {
CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
CLOCK_TYPE_MCPA, /* and so on */
CLOCK_TYPE_MCPT,
CLOCK_TYPE_PCM,
CLOCK_TYPE_PCMT,
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
CLOCK_TYPE_PCMT16,
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
CLOCK_TYPE_PDCT,
CLOCK_TYPE_ACPT,
CLOCK_TYPE_ASPTE,
CLOCK_TYPE_PMDACD2T,
CLOCK_TYPE_PCST,
CLOCK_TYPE_COUNT,
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
CLOCK_TYPE_NONE = -1, /* invalid clock type */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
};
enum {
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
CLOCK_MAX_MUX = 8 /* number of source options for each clock */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
};
/*
* Clock source mux for each clock type. This just converts our enum into
* a list of mux sources for use by the code.
*
* Note:
* The extra column in each clock source array is used to store the mask
* bits in its register for the source.
*/
#define CLK(x) CLOCK_ID_ ## x
static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_30},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_29},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
MASK_BITS_31_29},
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
ARM: tegra: rename MASK_BITS_29_28 to MASK_BITS_31_28 The only place where the MASK_BITS_* values are used is in adjust_periph_pll(), which interprets the value 4 (old MASK_BITS_29_28, new MASK_BITS_31_28) as being associated with mask OUT_CLK_SOURCE4_MASK, i.e. bits 31:28. Rename the MASK_BITS_ macro to reflect how it's actually implemented. Note that no Tegra clock register actually uses all of bits 31:28 as the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in those cases, nothing is stored in the bits above the mux field, so it's safe to pretend that the mux field extends all the way to the end of the register. As such, the U-Boot clock driver is currently a bit lazy, and doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps them all together and pretends they're all 31:28. This patch doesn't cause this issue; it was pre-existing. Hopefully, future patches will clean this up. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-01-24 17:16:18 +00:00
MASK_BITS_31_28}
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
};
/*
* Clock type for each peripheral clock source. We put the name in each
* record just so it is easy to match things up
*/
#define TYPE(name, type) type
static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
/* 0x00 */
TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
TYPE(PERIPHC_PWM, CLOCK_TYPE_PCST), /* only PWM uses b29:28 */
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SBC2, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SBC3, CLOCK_TYPE_PCMT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 0x08 */
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SBC1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 0x10 */
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
/* 0x18 */
TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 0x20 */
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT16),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
/* 0x28 */
TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SBC4, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 0x30 */
TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
/* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
TYPE(PERIPHC_G3D2, CLOCK_TYPE_MCPA),
TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PCST), /* s/b PCTS */
TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
TYPE(PERIPHC_I2C4, CLOCK_TYPE_PCMT16),
TYPE(PERIPHC_SBC5, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_SBC6, CLOCK_TYPE_PCMT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 0x40 */
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_AUDIO, CLOCK_TYPE_ACPT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_DAM0, CLOCK_TYPE_ACPT),
TYPE(PERIPHC_DAM1, CLOCK_TYPE_ACPT),
TYPE(PERIPHC_DAM2, CLOCK_TYPE_ACPT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PCST), /* MASK 31:30 */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
/* 0x48 */
TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PCST), /* MASK 31:30 */
TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SPEEDO, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 0x50 */
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT), /* offset 0x420h */
TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
TYPE(PERIPHC_HDA, CLOCK_TYPE_PCMT),
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
};
/*
* This array translates a periph_id to a periphc_internal_id
*
* Not present/matched up:
* uint vi_sensor; _VI_SENSOR_0, 0x1A8
* SPDIF - which is both 0x08 and 0x0c
*
*/
#define NONE(name) (-1)
#define OFFSET(name, value) PERIPHC_ ## name
static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
/* Low word: 31:0 */
NONE(CPU),
NONE(COP),
NONE(TRIGSYS),
NONE(RESERVED3),
NONE(RESERVED4),
NONE(TMR),
PERIPHC_UART1,
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
PERIPHC_UART2, /* and vfir 0x68 */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/* 8 */
NONE(GPIO),
PERIPHC_SDMMC2,
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
PERIPHC_I2S1,
PERIPHC_I2C1,
PERIPHC_NDFLASH,
PERIPHC_SDMMC1,
PERIPHC_SDMMC4,
/* 16 */
NONE(RESERVED16),
PERIPHC_PWM,
PERIPHC_I2S2,
PERIPHC_EPP,
PERIPHC_VI,
PERIPHC_G2D,
NONE(USBD),
NONE(ISP),
/* 24 */
PERIPHC_G3D,
NONE(RESERVED25),
PERIPHC_DISP2,
PERIPHC_DISP1,
PERIPHC_HOST1X,
NONE(VCP),
PERIPHC_I2S0,
NONE(CACHE2),
/* Middle word: 63:32 */
NONE(MEM),
NONE(AHBDMA),
NONE(APBDMA),
NONE(RESERVED35),
NONE(RESERVED36),
NONE(STAT_MON),
NONE(RESERVED38),
NONE(RESERVED39),
/* 40 */
NONE(KFUSE),
tegra30: add SBC1 to periph id mapping table SBC1 is SPI controller 1 on tegra30 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-29 13:51:25 +00:00
PERIPHC_SBC1,
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
PERIPHC_NOR,
NONE(RESERVED43),
PERIPHC_SBC2,
NONE(RESERVED45),
PERIPHC_SBC3,
PERIPHC_DVC_I2C,
/* 48 */
NONE(DSI),
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
PERIPHC_TVO, /* also CVE 0x40 */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
PERIPHC_MIPI,
PERIPHC_HDMI,
NONE(CSI),
PERIPHC_TVDAC,
PERIPHC_I2C2,
PERIPHC_UART3,
/* 56 */
NONE(RESERVED56),
PERIPHC_EMC,
NONE(USB2),
NONE(USB3),
PERIPHC_MPE,
PERIPHC_VDE,
NONE(BSEA),
NONE(BSEV),
/* Upper word 95:64 */
PERIPHC_SPEEDO,
PERIPHC_UART4,
PERIPHC_UART5,
PERIPHC_I2C3,
PERIPHC_SBC4,
PERIPHC_SDMMC3,
NONE(PCIE),
PERIPHC_OWR,
/* 72 */
NONE(AFI),
PERIPHC_CSITE,
NONE(PCIEXCLK),
NONE(AVPUCQ),
NONE(RESERVED76),
NONE(RESERVED77),
NONE(RESERVED78),
NONE(DTV),
/* 80 */
PERIPHC_NANDSPEED,
PERIPHC_I2CSLOW,
NONE(DSIB),
NONE(RESERVED83),
NONE(IRAMA),
NONE(IRAMB),
NONE(IRAMC),
NONE(IRAMD),
/* 88 */
NONE(CRAM2),
NONE(RESERVED89),
NONE(MDOUBLER),
NONE(RESERVED91),
NONE(SUSOUT),
NONE(RESERVED93),
NONE(RESERVED94),
NONE(RESERVED95),
/* V word: 31:0 */
NONE(CPUG),
NONE(CPULP),
PERIPHC_G3D2,
PERIPHC_MSELECT,
PERIPHC_TSENSOR,
PERIPHC_I2S3,
PERIPHC_I2S4,
PERIPHC_I2C4,
/* 08 */
PERIPHC_SBC5,
PERIPHC_SBC6,
PERIPHC_AUDIO,
NONE(APBIF),
PERIPHC_DAM0,
PERIPHC_DAM1,
PERIPHC_DAM2,
PERIPHC_HDA2CODEC2X,
/* 16 */
NONE(ATOMICS),
NONE(RESERVED17),
NONE(RESERVED18),
NONE(RESERVED19),
NONE(RESERVED20),
NONE(RESERVED21),
NONE(RESERVED22),
PERIPHC_ACTMON,
/* 24 */
NONE(RESERVED24),
NONE(RESERVED25),
NONE(RESERVED26),
NONE(RESERVED27),
PERIPHC_SATA,
PERIPHC_HDA,
NONE(RESERVED30),
NONE(RESERVED31),
/* W word: 31:0 */
NONE(HDA2HDMICODEC),
NONE(SATACOLD),
NONE(RESERVED0_PCIERX0),
NONE(RESERVED1_PCIERX1),
NONE(RESERVED2_PCIERX2),
NONE(RESERVED3_PCIERX3),
NONE(RESERVED4_PCIERX4),
NONE(RESERVED5_PCIERX5),
/* 40 */
NONE(CEC),
NONE(RESERVED6_PCIE2),
NONE(RESERVED7_EMC),
NONE(RESERVED8_HDMI),
NONE(RESERVED9_SATA),
NONE(RESERVED10_MIPI),
NONE(EX_RESERVED46),
NONE(EX_RESERVED47),
};
Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X. Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20. Thanks to Marcel Ziswiler for corrections to the T20/T30 values. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-06-25 16:50:44 +00:00
/*
* PLL divider shift/mask tables for all PLL IDs.
*/
struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
/*
* T30: some deviations from T2x.
* NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
* If lock_ena or lock_det are >31, they're not used in that PLL.
*/
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
.lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
.lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
.lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
{ .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
{ .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
.lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
{ .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
.lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
};
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/*
* Get the oscillator frequency, from the corresponding hardware configuration
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
* field. Note that T30 supports 3 new higher freqs, but we map back
* to the old T20 freqs. Support for the higher oscillators is TBD.
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
if (reg & 1) /* one of the newer freqs */
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
return reg >> 2; /* Map to most common (T20) freqs */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
}
/* Returns a pointer to the clock source register for a peripheral */
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
u32 *get_periph_source_reg(enum periph_id periph_id)
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
{
struct clk_rst_ctlr *clkrst =
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
enum periphc_internal_id internal_id;
/* Coresight is a special case */
if (periph_id == PERIPH_ID_CSI)
return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
internal_id = periph_id_to_internal_id[periph_id];
assert(internal_id != -1);
if (internal_id >= PERIPHC_VW_FIRST) {
internal_id -= PERIPHC_VW_FIRST;
return &clkrst->crc_clk_src_vw[internal_id];
} else
return &clkrst->crc_clk_src[internal_id];
}
ARM: tegra: add APIs the clock uclass driver will need A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:56 +00:00
int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
int *divider_bits, int *type)
{
enum periphc_internal_id internal_id;
if (!clock_periph_id_isvalid(periph_id))
return -1;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return -1;
*type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(*type))
return -1;
*mux_bits = clock_source[*type][CLOCK_MAX_MUX];
if (*type == CLOCK_TYPE_PCMT16)
*divider_bits = 16;
else
*divider_bits = 8;
return 0;
}
enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
{
enum periphc_internal_id internal_id;
int type;
if (!clock_periph_id_isvalid(periph_id))
return CLOCK_ID_NONE;
internal_id = periph_id_to_internal_id[periph_id];
if (!periphc_internal_id_isvalid(internal_id))
return CLOCK_ID_NONE;
type = clock_periph_type[internal_id];
if (!clock_type_id_isvalid(type))
return CLOCK_ID_NONE;
return clock_source[type][source];
}
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/**
* Given a peripheral ID and the required source clock, this returns which
* value should be programmed into the source mux for that peripheral.
*
* There is special code here to handle the one source type with 5 sources.
*
* @param periph_id peripheral to start
* @param source PLL id of required parent clock
* @param mux_bits Set to number of bits in mux register: 2 or 4
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
* @param divider_bits Set to number of divider bits (8 or 16)
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
* @return mux value (0-4, or -1 if not found)
*/
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
int get_periph_clock_source(enum periph_id periph_id,
enum clock_id parent, int *mux_bits, int *divider_bits)
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
{
enum clock_type_id type;
ARM: tegra: add APIs the clock uclass driver will need A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:56 +00:00
int mux, err;
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
ARM: tegra: add APIs the clock uclass driver will need A future patch will implement a clock uclass driver for Tegra. That driver will call into Tegra's existing clock code to simplify the transition; this avoids tieing the clock uclass patches into significant refactoring of the existing custom clock API implementation. Some of the Tegra clock APIs that manipulate peripheral clocks require both the peripheral clock ID and parent clock ID to be passed in together. However, the clock uclass API does not require any such "parent" parameter, so the clock driver must determine this information itself. This patch implements new Tegra- specific clock API clock_get_periph_parent() for this purpose. The new API is implemented in the core Tegra clock code rather than SoC- specific clock code. The implementation uses various SoC-/clock-specific data. That data is only available in SoC-specific clock code. Consequently, two new internal APIs are added that enable the core clock code to retrieve this information from the SoC-specific clock code. Due to the structure of the Tegra clock code, this leads to some unfortunate code duplication. However, this situation predates this patch. Ideally, future work will de-duplicate the Tegra clock code, and migrate it into drivers/clk/tegra. However, such refactoring is kept separate from this series. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:56 +00:00
err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
assert(!err);
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
if (clock_source[type][mux] == parent)
return mux;
/* if we get here, either us or the caller has made a mistake */
printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
parent);
return -1;
}
void clock_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 *clk;
u32 reg;
/* Enable/disable the clock to this peripheral */
assert(clock_periph_id_isvalid(periph_id));
if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
else
clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
reg = readl(clk);
if (enable)
reg |= PERIPH_MASK(periph_id);
else
reg &= ~PERIPH_MASK(periph_id);
writel(reg, clk);
}
void reset_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 *reset;
u32 reg;
/* Enable/disable reset to the peripheral */
assert(clock_periph_id_isvalid(periph_id));
if (periph_id < PERIPH_ID_VW_FIRST)
reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
else
reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
reg = readl(reset);
if (enable)
reg |= PERIPH_MASK(periph_id);
else
reg &= ~PERIPH_MASK(periph_id);
writel(reg, reset);
}
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-11 22:31:55 +00:00
#if CONFIG_IS_ENABLED(OF_CONTROL)
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
/*
* Convert a device tree clock ID to our peripheral ID. They are mostly
* the same but we are very cautious so we check that a valid clock ID is
* provided.
*
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
* @param clk_id Clock ID according to tegra30 device tree binding
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
*/
Tegra: Move common clock code to arch/arm/cpu/tegra-common/clock.c This 'commonizes' much of the clock/pll code. SoC-dependent code and tables are left in arch/cpu/tegraXXX-common/clock.c Some T30 tables needed whitespace fixes due to checkpatch complaints. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-01-23 21:01:01 +00:00
enum periph_id clk_id_to_periph_id(int clk_id)
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
{
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
if (clk_id > PERIPH_ID_COUNT)
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
return PERIPH_ID_NONE;
switch (clk_id) {
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
case PERIPH_ID_RESERVED3:
case PERIPH_ID_RESERVED4:
case PERIPH_ID_RESERVED16:
case PERIPH_ID_RESERVED24:
case PERIPH_ID_RESERVED35:
case PERIPH_ID_RESERVED43:
case PERIPH_ID_RESERVED45:
case PERIPH_ID_RESERVED56:
ARM: tegra: Provide PCIEXCLK reset ID This reset is required for PCIe and the corresponding ID therefore needs to be defined. The enumeration value for this was properly defined on some SoCs but not on others. Similarly, some contained it in the mapping of peripheral IDs to clock IDs, other didn't. This patch defines it consistently for all supported SoC generations. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-10 05:25:07 +00:00
case PERIPH_ID_PCIEXCLK:
Tegra30: clocks: Fix clock tables for I2C and other periphs Add 16-bit divider support (I2C) to periph table, annotate and correct some entries, and fix clk_id lookup function. Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-12-21 22:02:45 +00:00
case PERIPH_ID_RESERVED76:
case PERIPH_ID_RESERVED77:
case PERIPH_ID_RESERVED78:
case PERIPH_ID_RESERVED83:
case PERIPH_ID_RESERVED89:
case PERIPH_ID_RESERVED91:
case PERIPH_ID_RESERVED93:
case PERIPH_ID_RESERVED94:
case PERIPH_ID_RESERVED95:
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
return PERIPH_ID_NONE;
default:
return clk_id;
}
}
of: clean up OF_CONTROL ifdef conditionals We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-11 22:31:55 +00:00
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
void clock_early_init(void)
{
ARM: tegra: don't exceed AVP limits when configuring PLLP Based on the Tegra TRM, the system clock (which is the AVP clock) can run up to 275MHz. On power on, the default sytem clock source is set to PLLP_OUT0. In function clock_early_init(), PLLP_OUT0 will be set to 408MHz which is beyond system clock's upper limit. The fix is to set the system clock to CLK_M before initializing PLLP, and then switch back to PLLP_OUT4, which has an appropriate divider configured, after PLLP has been configured Implement this logic in new function tegra30_set_up_pllp(), which sets up PLLP and all PLLP_OUT* dividers, and handles the AVP clock switching. Remove the duplicate PLLP setup from pllx_set_rate() and adjust_pllp_out_freqs(). Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> [swarren, significantly refactored the change] Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-01-24 17:37:36 +00:00
tegra30_set_up_pllp();
Tegra30: Add common CPU (shared) files These files are used by both SPL and main U-Boot. Also made minor changes to shared Tegra code to support T30 differences. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2012-12-11 13:34:15 +00:00
}
Tegra114: Initialize System Counter (TSC) with osc frequency T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-04-01 22:48:54 +00:00
void arch_timer_init(void)
{
}
ARM: tegra: Implement tegra_plle_enable() This function is required by PCIe and SATA. This patch implements it on Tegra20, Tegra30 and Tegra124. It isn't implemented for Tegra114 because it doesn't support PCIe or SATA. Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-10 05:25:06 +00:00
#define PMC_SATA_PWRGT 0x1ac
#define PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE (1 << 5)
#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1 << 4)
#define PLLE_SS_CNTL 0x68
#define PLLE_SS_CNTL_SSCINCINTRV(x) (((x) & 0x3f) << 24)
#define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
#define PLLE_SS_CNTL_SSCBYP (1 << 12)
#define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
#define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
#define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
#define PLLE_BASE 0x0e8
#define PLLE_BASE_ENABLE_CML (1 << 31)
#define PLLE_BASE_ENABLE (1 << 30)
#define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
#define PLLE_BASE_PLDIV(x) (((x) & 0x3f) << 16)
#define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
#define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
#define PLLE_MISC 0x0ec
#define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16)
#define PLLE_MISC_PLL_READY (1 << 15)
#define PLLE_MISC_LOCK (1 << 11)
#define PLLE_MISC_LOCK_ENABLE (1 << 9)
#define PLLE_MISC_SETUP_EXT(x) (((x) & 0x3) << 2)
static int tegra_plle_train(void)
{
unsigned int timeout = 2000;
unsigned long value;
value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
value |= PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
value |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
value = readl(NV_PA_PMC_BASE + PMC_SATA_PWRGT);
value &= ~PMC_SATA_PWRGT_PLLE_IDDQ_OVERRIDE;
writel(value, NV_PA_PMC_BASE + PMC_SATA_PWRGT);
do {
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
if (value & PLLE_MISC_PLL_READY)
break;
udelay(100);
} while (--timeout);
if (timeout == 0) {
error("timeout waiting for PLLE to become ready");
return -ETIMEDOUT;
}
return 0;
}
int tegra_plle_enable(void)
{
unsigned int cpcon = 11, p = 18, n = 150, m = 1, timeout = 1000;
u32 value;
int err;
/* disable PLLE clock */
value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
value &= ~PLLE_BASE_ENABLE_CML;
value &= ~PLLE_BASE_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
/* clear lock enable and setup field */
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
value &= ~PLLE_MISC_LOCK_ENABLE;
value &= ~PLLE_MISC_SETUP_BASE(0xffff);
value &= ~PLLE_MISC_SETUP_EXT(0x3);
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
if ((value & PLLE_MISC_PLL_READY) == 0) {
err = tegra_plle_train();
if (err < 0) {
error("failed to train PLLE: %d", err);
return err;
}
}
/* configure PLLE */
value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
value &= ~PLLE_BASE_PLDIV_CML(0x0f);
value |= PLLE_BASE_PLDIV_CML(cpcon);
value &= ~PLLE_BASE_PLDIV(0x3f);
value |= PLLE_BASE_PLDIV(p);
value &= ~PLLE_BASE_NDIV(0xff);
value |= PLLE_BASE_NDIV(n);
value &= ~PLLE_BASE_MDIV(0xff);
value |= PLLE_BASE_MDIV(m);
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
value |= PLLE_MISC_SETUP_BASE(0x7);
value |= PLLE_MISC_LOCK_ENABLE;
value |= PLLE_MISC_SETUP_EXT(0);
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
PLLE_SS_CNTL_BYPASS_SS;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
value |= PLLE_BASE_ENABLE_CML | PLLE_BASE_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
do {
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
if (value & PLLE_MISC_LOCK)
break;
udelay(2);
} while (--timeout);
if (timeout == 0) {
error("timeout waiting for PLLE to lock");
return -ETIMEDOUT;
}
udelay(50);
value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
value &= ~PLLE_SS_CNTL_SSCINCINTRV(0x3f);
value |= PLLE_SS_CNTL_SSCINCINTRV(0x18);
value &= ~PLLE_SS_CNTL_SSCINC(0xff);
value |= PLLE_SS_CNTL_SSCINC(0x01);
value &= ~PLLE_SS_CNTL_SSCBYP;
value &= ~PLLE_SS_CNTL_INTERP_RESET;
value &= ~PLLE_SS_CNTL_BYPASS_SS;
value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
value |= PLLE_SS_CNTL_SSCMAX(0x24);
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
return 0;
}
ARM: tegra: add peripheral clock init table Currently, Tegra peripheral drivers control two aspects of their HW module clock(s): 1) The clock enable/rate for the peripheral clock itself. 2) The system-level clock tree setup, i.e. the clock parent. Aspect 1 is reasonable, but aspect 2 is a system-level decision, not something that an individual peripheral driver should in general know about or influence. Such system-level knowledge ties the driver to a specific SoC implementation, even when they use generic APIs for clock manipulation, since they must have SoC-specific knowledge such as parent clock IDs. Limited exceptions exist, such as where peripheral HW is expected to dynamically switch between clock sources at run-time, such as CPU clock scaling or display clock conflict management in a multi-head scenario. This patch enhances the Tegra core code to perform system-level clock tree setup, in a similar fashion to the Linux kernel Tegra clock driver. This will allow future patches to simplify peripheral drivers by removing the clock parent setup logic. This change is required prior to converting peripheral drivers to use the standard clock APIs, since: 1) The clock uclass doesn't currently support a set_parent() operation. Adding one is possible, but not necessary at the moment. 2) The clock APIs retrieve all clock IDs from device tree, and the DT bindings for almost all peripherals only includes information about the relevant peripheral clocks, and not any potential parent clocks. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:55 +00:00
struct periph_clk_init periph_clk_init_table[] = {
{ PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
{ PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
{ PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
{ PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
{ PERIPH_ID_NDFLASH, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
{ PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
{ PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
{ PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
{ PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
{ -1, },
};
Reference in a new issue Copy permalink