2021-08-07 08:01:13 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2020 NXP
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*/
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#ifndef __IMX8ULP_EVK_H
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#define __IMX8ULP_EVK_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_MALLOC_F_ADDR 0x22040000
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#endif
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/* ENET Config */
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#if defined(CONFIG_FEC_MXC)
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#define PHY_ANEG_TIMEOUT 20000
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#define CONFIG_FEC_MXC_PHYADDR 1
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#endif
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#ifdef CONFIG_DISTRO_DEFAULTS
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0)
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#include <config_distro_bootcmd.h>
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#else
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#define BOOTENV
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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2021-08-23 14:25:30 +00:00
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"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
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2021-08-07 08:01:13 +00:00
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"image=Image\0" \
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"console=ttyLP1,115200 earlycon\0" \
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"fdt_addr_r=0x83000000\0" \
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"boot_fit=no\0" \
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"fdtfile=imx8ulp-evk.dtb\0" \
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"initrd_addr=0x83800000\0" \
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"bootm_size=0x10000000\0" \
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2021-12-11 19:55:52 +00:00
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"mmcpart=1\0" \
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2022-04-15 04:23:41 +00:00
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"mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
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2021-08-07 08:01:13 +00:00
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/* Link Definitions */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM 0x80000000
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#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
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/* Using ULP WDOG for reset */
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#define WDOG_BASE_ADDR WDG3_RBASE
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#endif
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