mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-24 13:43:28 +00:00
configs: drop CONFIG_MMCROOT
CONFIG_MMCROOT is only used to set mmcroot, no need a dedicated macro. Script as below " for i in `ls include/configs/*.h` do mmcroot=`sed -n '/define.*MMCROOT/ p' $i | awk -F\" '{ print $2;}'` if [ ! -n "$mmcroot" ]; then continue fi sed -i '/define.*MMCROOT/ d' $i sed -i 's,\" CONFIG_MMCROOT \",'$mmcroot',g' $i done " Reviewed-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
parent
c82622acdf
commit
adfaa4284c
27 changed files with 23 additions and 51 deletions
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@ -26,7 +26,6 @@
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#include "mx6_common.h"
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#define CONFIG_MMCROOT "/dev/mmcblk0p1"
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
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@ -183,7 +182,7 @@
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"${pubkey}\0" \
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"mainRargs=setenv bootargs console=${console},${baudrate} " \
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"rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"mmcRargs=setenv bootargs console=${console},${baudrate} " \
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@ -109,7 +109,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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/* On CCP board, USDHC1 is for eMMC */
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#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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@ -78,7 +78,7 @@
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"fdt_file=imx8qm-cgt-qmx8.dtb\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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@ -122,7 +122,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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@ -104,7 +104,6 @@
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
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#endif
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/* USB Configs */
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@ -31,7 +31,7 @@
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"fdt_addr=0x83000000\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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@ -83,7 +83,6 @@
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
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/* USB Configs */
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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@ -88,7 +88,7 @@
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"bootm_size=0x10000000\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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@ -140,7 +140,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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@ -52,7 +52,7 @@
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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@ -63,7 +63,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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@ -51,7 +51,7 @@
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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@ -62,7 +62,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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@ -61,7 +61,7 @@
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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@ -72,7 +72,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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/* Totally 6GB DDR */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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@ -104,7 +104,7 @@
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"bootm_size=0x10000000\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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@ -155,7 +155,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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/* Totally 6GB or 4G DDR */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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@ -55,7 +55,7 @@
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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@ -66,7 +66,6 @@
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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@ -62,7 +62,7 @@
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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@ -52,7 +52,7 @@
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"initrd_high=0xffffffffffffffff\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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@ -50,7 +50,7 @@
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"initrd_high=0xffffffffffffffff\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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/* Default environment is in SD */
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/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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"initrd_addr=0x83800000\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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* USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND,
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* USDHC2 is for SD, USDHC3 is for SD on base board
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*/
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#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
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#define CONFIG_SYS_FSL_USDHC_NUM 3
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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@ -48,7 +48,7 @@
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"initrd_high=0xffffffffffffffff\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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/* Default environment is in SD */
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/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM_1 0x80000000
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"initrd_addr=0x83800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk2p2"
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define PHYS_SDRAM 0x80000000
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"ip_dyn=yes\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* FLASH and environment organization */
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#define CONFIG_MMCROOT "/dev/mmcblk0p2"
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/* USB Configs */
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#ifdef CONFIG_CMD_USB
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"ip_dyn=yes\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Environment organization */
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#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
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"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* environment organization */
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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/* USB Configs */
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#ifdef CONFIG_CMD_USB
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"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* environment organization */
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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#define CONFIG_IOMUX_LPSR
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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#define CONFIG_MMCROOT "/dev/mmcblk0p2"
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/* Using ULP WDOG for reset */
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#define WDOG_BASE_ADDR WDG1_RBASE
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"fdt_addr=0x63000000\0" \
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
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"mmcpart=1\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
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"mmcargs=setenv bootargs console=${console},${baudrate} " \
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"root=${mmcroot}\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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#define CONFIG_SYS_BOOTM_LEN 0x1000000
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||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
/* Using ULP WDOG for reset */
|
||||
#define WDOG_BASE_ADDR WDG1_RBASE
|
||||
|
@ -47,7 +46,7 @@
|
|||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
|
|
|
@ -77,7 +77,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
|
|
|
@ -77,7 +77,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=" \
|
||||
|
@ -80,7 +80,6 @@
|
|||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Environment is in stored in the eMMC boot partition */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
|
@ -61,7 +60,7 @@
|
|||
"ip_dyn=yes\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
|
|
Loading…
Reference in a new issue