mirror of
https://github.com/AsahiLinux/u-boot
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arm: imx: add i.MX8ULP EVK support
Add i.MX8ULP EVK basic support, support SD/I2C/ENET/LPUART Log as below: I would keep some debug info for now, and after we move to be stable and production launch, we could drop that. U-Boot SPL 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) Normal Boot upower_init: soc_id=48 upower_init: version:11.11.6 upower_init: start uPower RAM service user_upwr_rdy_callb: soc=b user_upwr_rdy_callb: RAM version:12.6 Turn on switches ok Turn on memories ok Clear DDR retention ok Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F0 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. Poll for freq_chg_req on SIM register and change to F1 frequency. Poll for freq_chg_req on SIM register and change to F2 frequency. complete De-Skew PLL is locked and ready WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x3a800 by ROM_API NOTICE: BL31: v2.4(release):imx_5.10.35_2.0.0_imx8ulp_er-10-gf37e59b94 NOTICE: BL31: Built : 01:56:58, Jun 29 2021 NOTICE: upower_init: start uPower RAM service NOTICE: user_upwr_rdy_callb: soc=b NOTICE: user_upwr_rdy_callb: RAM version:12.6 U-Boot 2021.07-rc4-00164-gb800e19a6b (Jun 29 2021 - 10:23:30 +0800) CPU: Freescale i.MX8ULP rev1.0 at 744 MHz Reset cause: POR Boot mode: Single boot Model: FSL i.MX8ULP EVK DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@293a0000 Out: serial@293a0000 Err: serial@293a0000 Net: Warning: ethernet@29950000 (eth0) using random MAC address - 96:35:88:62:e0:44 eth0: ethernet@29950000 Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
6beec0e78c
commit
3f2b4d7220
13 changed files with 2047 additions and 0 deletions
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@ -862,6 +862,9 @@ dtb-$(CONFIG_ARCH_IMX8) += \
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imx8-deneb.dtb \
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imx8-giedi.dtb
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dtb-$(CONFIG_ARCH_IMX8ULP) += \
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imx8ulp-evk.dtb
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dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-evk.dtb \
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imx8mm-icore-mx8mm-ctouch2.dtb \
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40
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
Normal file
40
arch/arm/dts/imx8ulp-evk-u-boot.dtsi
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@ -0,0 +1,40 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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&{/soc@0} {
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u-boot,dm-spl;
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};
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&per_bridge3 {
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u-boot,dm-spl;
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};
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&per_bridge4 {
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u-boot,dm-spl;
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};
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&iomuxc1 {
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u-boot,dm-spl;
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};
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&pinctrl_lpuart5 {
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u-boot,dm-spl;
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};
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&s400_mu {
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u-boot,dm-spl;
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};
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&lpuart5 {
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u-boot,dm-spl;
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};
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&usdhc0 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc0 {
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u-boot,dm-spl;
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};
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223
arch/arm/dts/imx8ulp-evk.dts
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223
arch/arm/dts/imx8ulp-evk.dts
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@ -0,0 +1,223 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2021 NXP
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*/
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/dts-v1/;
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#include "imx8ulp.dtsi"
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/ {
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model = "FSL i.MX8ULP EVK";
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compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
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chosen {
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stdout-path = &lpuart5;
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bootargs = "console=ttyLP1,115200 earlycon";
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};
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usdhc2_pwrseq: usdhc2_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
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};
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};
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&lpuart5 {
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/* console */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpuart5>;
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pinctrl-1 = <&pinctrl_lpuart5>;
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status = "okay";
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};
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&iomuxc1 {
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX8ULP_PAD_PTF14__LPUART5_TX 0x03
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MX8ULP_PAD_PTF15__LPUART5_RX 0x03
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>;
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};
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pinctrl_lpi2c7: lpi2c7grp {
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fsl,pins = <
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MX8ULP_PAD_PTE12__LPI2C7_SCL 0x27
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MX8ULP_PAD_PTE13__LPI2C7_SDA 0x27
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>;
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};
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pinctrl_usdhc0: usdhc0grp {
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fsl,pins = <
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MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x43
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MX8ULP_PAD_PTD1__SDHC0_CMD 0x43
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MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042
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MX8ULP_PAD_PTD10__SDHC0_D0 0x43
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MX8ULP_PAD_PTD9__SDHC0_D1 0x43
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MX8ULP_PAD_PTD8__SDHC0_D2 0x43
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MX8ULP_PAD_PTD7__SDHC0_D3 0x43
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MX8ULP_PAD_PTD6__SDHC0_D4 0x43
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MX8ULP_PAD_PTD5__SDHC0_D5 0x43
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MX8ULP_PAD_PTD4__SDHC0_D6 0x43
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MX8ULP_PAD_PTD3__SDHC0_D7 0x43
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MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042
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>;
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};
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pinctrl_usdhc2_pte: usdhc2ptegrp {
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fsl,pins = <
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MX8ULP_PAD_PTE1__SDHC2_D0 0x43
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MX8ULP_PAD_PTE0__SDHC2_D1 0x43
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MX8ULP_PAD_PTE5__SDHC2_D2 0x43
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MX8ULP_PAD_PTE4__SDHC2_D3 0x43
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MX8ULP_PAD_PTE2__SDHC2_CLK 0x10042
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MX8ULP_PAD_PTE3__SDHC2_CMD 0x43
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MX8ULP_PAD_PTE7__PTE7 0x10003
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX8ULP_PAD_PTE14__ENET0_MDIO 0x43
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MX8ULP_PAD_PTE15__ENET0_MDC 0x43
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MX8ULP_PAD_PTE18__ENET0_CRS_DV 0x43
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MX8ULP_PAD_PTE17__ENET0_RXER 0x43
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MX8ULP_PAD_PTF1__ENET0_RXD0 0x43
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MX8ULP_PAD_PTE20__ENET0_RXD1 0x43
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MX8ULP_PAD_PTE16__ENET0_TXEN 0x43
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MX8ULP_PAD_PTE23__ENET0_TXD0 0x43
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MX8ULP_PAD_PTE22__ENET0_TXD1 0x43
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MX8ULP_PAD_PTE19__ENET0_REFCLK 0x10043
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MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
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>;
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};
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pinctrl_usbotg0_id: otg0idgrp {
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fsl,pins = <
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MX8ULP_PAD_PTF2__USB0_ID 0x10003
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>;
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};
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pinctrl_usbotg1_id: otg1idgrp {
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fsl,pins = <
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MX8ULP_PAD_PTD23__USB1_ID 0x10003
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>;
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};
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};
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&usdhc0 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc0>;
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pinctrl-1 = <&pinctrl_usdhc0>;
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pinctrl-2 = <&pinctrl_usdhc0>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc2_pte>;
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pinctrl-1 = <&pinctrl_usdhc2_pte>;
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pinctrl-2 = <&pinctrl_usdhc2_pte>;
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pinctrl-3 = <&pinctrl_usdhc2_pte>;
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mmc-pwrseq = <&usdhc2_pwrseq>;
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max-frequency = <100000000>;
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bus-width = <4>;
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keep-power-in-suspend;
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non-removable;
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wakeup-source;
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status = "okay";
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wifi_wake_host {
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compatible = "nxp,wifi-wake-host";
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interrupt-parent = <&gpioe>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "host-wake";
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};
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};
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&lpi2c7 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c7>;
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status = "okay";
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pcal6408: gpio@21 {
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compatible = "ti,tca6408";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&flexspi0 {
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status = "okay";
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flash0: atxp032@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <66000000>;
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};
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};
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&flexspi2 {
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status = "okay";
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flash1: mt35xu512aba@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <8>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-handle = <ðphy>;
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status = "okay";
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phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&usbotg0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg0_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbphy0 {
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fsl,tx-d-cal = <88>;
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1_id>;
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbphy1 {
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fsl,tx-d-cal = <88>;
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};
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@ -11,6 +11,13 @@ choice
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prompt "i.MX8ULP board select"
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optional
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config TARGET_IMX8ULP_EVK
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bool "imx8ulp_evk"
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select IMX8ULP
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select SUPPORT_SPL
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endchoice
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source "board/freescale/imx8ulp_evk/Kconfig"
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endif
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14
board/freescale/imx8ulp_evk/Kconfig
Normal file
14
board/freescale/imx8ulp_evk/Kconfig
Normal file
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@ -0,0 +1,14 @@
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if TARGET_IMX8ULP_EVK
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config SYS_BOARD
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default "imx8ulp_evk"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "imx8ulp_evk"
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source "board/freescale/common/Kconfig"
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endif
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6
board/freescale/imx8ulp_evk/MAINTAINERS
Normal file
6
board/freescale/imx8ulp_evk/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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i.MX8ULP EVK BOARD
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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F: board/freescale/imx8ulp_evk/
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F: include/configs/imx8ulp_evk.h
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F: configs/imx8ulp_evk_defconfig
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7
board/freescale/imx8ulp_evk/Makefile
Normal file
7
board/freescale/imx8ulp_evk/Makefile
Normal file
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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obj-y += imx8ulp_evk.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o ddr_init.o lpddr4_timing.o
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endif
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207
board/freescale/imx8ulp_evk/ddr_init.c
Normal file
207
board/freescale/imx8ulp_evk/ddr_init.c
Normal file
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@ -0,0 +1,207 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx-regs.h>
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#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR)
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#define CTL_START 0x1
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#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
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#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
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#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
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#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
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#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
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#define DFI_INIT_COMPLETE 0x2
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#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
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#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
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#define DENALI_PI_00 (DDR_PI_BASE_ADDR)
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#define PI_START 0x1
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#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4)
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#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11)
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#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12)
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#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
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#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25)
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#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624)
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#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537)
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#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8)
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#define PHY_FREQ_SEL_INDEX(X) ((X) << 16)
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#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547)
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#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555)
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#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564)
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#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565)
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int ddr_calibration(unsigned int fsp_table[3])
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{
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u32 reg_val;
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u32 int_status_init, phy_freq_req, phy_freq_type;
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u32 lock_0, lock_1, lock_2;
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u32 freq_chg_pt, freq_chg_cnt;
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reg_val = readl(DENALI_CTL_250);
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if (((reg_val >> 16) & 0x3) == 1)
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freq_chg_cnt = 2;
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else
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freq_chg_cnt = 3;
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reg_val = readl(DENALI_PI_12);
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if (reg_val == 0x3) {
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freq_chg_pt = 1;
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} else if (reg_val == 0x7) {
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freq_chg_pt = 2;
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} else {
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printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val);
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return -1;
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}
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debug("%s\n", __func__);
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/* Assert PI_START parameter and then assert START parameter in Controller. */
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reg_val = readl(DENALI_PI_00) | PI_START;
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writel(reg_val, DENALI_PI_00);
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reg_val = readl(DENALI_CTL_00) | CTL_START;
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writel(reg_val, DENALI_CTL_00);
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/* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */
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do {
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if (!freq_chg_cnt) {
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int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff;
|
||||
/* DDR subsystem is ready for traffic. */
|
||||
if (int_status_init & DFI_INIT_COMPLETE) {
|
||||
printf("complete\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* During leveling, PHY will request for freq change and SoC clock
|
||||
* logic should provide requested frequency, Polling SIM LPDDR_CTRL2
|
||||
* Bit phy_freq_chg_req until be 1'b1
|
||||
*/
|
||||
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
|
||||
phy_freq_req = (reg_val >> 7) & 0x1;
|
||||
|
||||
if (phy_freq_req) {
|
||||
phy_freq_type = reg_val & 0x1F;
|
||||
if (!phy_freq_type) {
|
||||
printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n");
|
||||
set_ddr_clk(fsp_table[phy_freq_type] >> 1);
|
||||
|
||||
/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
|
||||
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
|
||||
writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
|
||||
} else if (phy_freq_type == 0x01) {
|
||||
printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n");
|
||||
set_ddr_clk(fsp_table[phy_freq_type] >> 1);
|
||||
|
||||
/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
|
||||
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
|
||||
writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
|
||||
if (freq_chg_pt == 1)
|
||||
freq_chg_cnt--;
|
||||
} else if (phy_freq_type == 0x02) {
|
||||
printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n");
|
||||
set_ddr_clk(fsp_table[phy_freq_type] >> 1);
|
||||
|
||||
/* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */
|
||||
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
|
||||
writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2);
|
||||
if (freq_chg_pt == 2)
|
||||
freq_chg_cnt--;
|
||||
}
|
||||
reg_val = readl(AVD_SIM_LPDDR_CTRL2);
|
||||
}
|
||||
} while (1);
|
||||
|
||||
/* Check PLL lock status */
|
||||
lock_0 = readl(DENALI_PHY_1564) & 0xffff;
|
||||
lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff;
|
||||
lock_2 = readl(DENALI_PHY_1565) & 0xffff;
|
||||
|
||||
if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) {
|
||||
printf("De-Skew PLL failed to lock\n");
|
||||
printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2);
|
||||
return -1;
|
||||
}
|
||||
|
||||
printf("De-Skew PLL is locked and ready\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ddr_init(struct dram_timing_info2 *dram_timing)
|
||||
{
|
||||
int i;
|
||||
|
||||
debug("%s\n", __func__);
|
||||
|
||||
set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */
|
||||
|
||||
/* Initialize CTL registers */
|
||||
for (i = 0; i < dram_timing->ctl_cfg_num; i++)
|
||||
writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg);
|
||||
|
||||
/* Initialize PI registers */
|
||||
for (i = 0; i < dram_timing->pi_cfg_num; i++)
|
||||
writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg);
|
||||
|
||||
/* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */
|
||||
writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
|
||||
for (i = 0; i < dram_timing->phy_f1_cfg_num; i++)
|
||||
writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg);
|
||||
|
||||
/* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */
|
||||
writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537);
|
||||
for (i = 0; i < dram_timing->phy_f2_cfg_num; i++)
|
||||
writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg);
|
||||
|
||||
/* Re-enable MULTICAST mode */
|
||||
writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537);
|
||||
|
||||
return ddr_calibration(dram_timing->fsp_table);
|
||||
}
|
||||
|
||||
void enable_bypass_mode(void)
|
||||
{
|
||||
u32 reg_val;
|
||||
|
||||
/* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */
|
||||
reg_val = readl(DENALI_PI_04) & ~0x1;
|
||||
writel(reg_val, DENALI_PI_04);
|
||||
|
||||
/* PI_FREQ_MAP=0x1 (DENALI_PI_12) */
|
||||
writel(0x1, DENALI_PI_12);
|
||||
|
||||
/* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */
|
||||
reg_val = readl(DENALI_PI_11) & ~(0x1f << 8);
|
||||
writel(reg_val, DENALI_PI_11);
|
||||
|
||||
/* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */
|
||||
reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24);
|
||||
writel(reg_val, DENALI_CTL_23);
|
||||
|
||||
/* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */
|
||||
reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8);
|
||||
writel(reg_val, DENALI_PHY_1547);
|
||||
|
||||
/* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */
|
||||
reg_val = readl(DENALI_PHY_1624) | 0x1;
|
||||
writel(reg_val, DENALI_PHY_1624);
|
||||
|
||||
/* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */
|
||||
reg_val = readl(DENALI_PHY_1555) | 0x1;
|
||||
writel(reg_val, DENALI_PHY_1555);
|
||||
|
||||
/* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */
|
||||
reg_val = 0x020100;
|
||||
writel(reg_val, DENALI_CTL_25);
|
||||
}
|
||||
67
board/freescale/imx8ulp_evk/imx8ulp_evk.c
Normal file
67
board/freescale/imx8ulp_evk/imx8ulp_evk.c
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2020 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/imx8ulp-pins.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/pcc.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||
#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE)
|
||||
static iomux_cfg_t const enet_clk_pads[] = {
|
||||
IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
||||
IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
|
||||
};
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
/*
|
||||
* Since ref clock and timestamp clock are from external,
|
||||
* set the iomux prior the clock enablement
|
||||
*/
|
||||
imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads));
|
||||
|
||||
/* Select enet time stamp clock: 001 - External Timestamp Clock */
|
||||
cgc1_enet_stamp_sel(1);
|
||||
|
||||
/* enable FEC PCC */
|
||||
pcc_clock_enable(4, ENET_PCC4_SLOT, true);
|
||||
pcc_reset_peripheral(4, ENET_PCC4_SLOT, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_FEC_MXC))
|
||||
setup_fec();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
1158
board/freescale/imx8ulp_evk/lpddr4_timing.c
Normal file
1158
board/freescale/imx8ulp_evk/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load diff
105
board/freescale/imx8ulp_evk/spl.c
Normal file
105
board/freescale/imx8ulp_evk/spl.c
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <errno.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx8ulp-pins.h>
|
||||
#include <dm/uclass.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/device-internal.h>
|
||||
#include <dm/lists.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/rdc.h>
|
||||
#include <asm/arch/upower.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
init_clk_ddr();
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return BOOT_DEVICE_BOOTROM;
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
u32 pmic_reg;
|
||||
|
||||
/* PMIC set bucks1-4 to PWM mode */
|
||||
upower_pmic_i2c_read(0x10, &pmic_reg);
|
||||
upower_pmic_i2c_read(0x14, &pmic_reg);
|
||||
upower_pmic_i2c_read(0x21, &pmic_reg);
|
||||
upower_pmic_i2c_read(0x2e, &pmic_reg);
|
||||
|
||||
upower_pmic_i2c_write(0x10, 0x3d);
|
||||
upower_pmic_i2c_write(0x14, 0x7d);
|
||||
upower_pmic_i2c_write(0x21, 0x7d);
|
||||
upower_pmic_i2c_write(0x2e, 0x3d);
|
||||
|
||||
upower_pmic_i2c_read(0x10, &pmic_reg);
|
||||
upower_pmic_i2c_read(0x14, &pmic_reg);
|
||||
upower_pmic_i2c_read(0x21, &pmic_reg);
|
||||
upower_pmic_i2c_read(0x2e, &pmic_reg);
|
||||
|
||||
/* Set buck3 to 1.1v OD */
|
||||
upower_pmic_i2c_write(0x22, 0x28);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void spl_board_init(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
|
||||
uclass_find_first_device(UCLASS_MISC, &dev);
|
||||
|
||||
for (; dev; uclass_find_next_device(&dev)) {
|
||||
if (device_probe(dev))
|
||||
continue;
|
||||
}
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
puts("Normal Boot\n");
|
||||
|
||||
/* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */
|
||||
|
||||
upower_init();
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
|
||||
/* This must place after upower init, so access to MDA and MRC are valid */
|
||||
/* Init XRDC MDA */
|
||||
xrdc_init_mda();
|
||||
|
||||
/* Init XRDC MRC for VIDEO, DSP domains */
|
||||
xrdc_init_mrc();
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Clear the BSS. */
|
||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||
|
||||
timer_init();
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
}
|
||||
103
configs/imx8ulp_evk_defconfig
Normal file
103
configs/imx8ulp_evk_defconfig
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8ULP=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80200000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_TARGET_IMX8ULP_EVK=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_TEXT_BASE=0x22020000
|
||||
CONFIG_SPL_LOAD_IMX_CONTAINER=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_BOOTDELAY=0
|
||||
CONFIG_DEFAULT_FDT_FILE="imx8ulp-evk"
|
||||
CONFIG_SPL_BOARD_INIT=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
#CONFIG_SPL_RAM_SUPPORT=y
|
||||
#CONFIG_SPL_RAM_DEVICE=y
|
||||
#CONFIG_SPL_MMC_SUPPORT=y
|
||||
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000
|
||||
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8ulp-evk"
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8ULP=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
|
||||
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_READ=y
|
||||
CONFIG_BAUDRATE=115200
|
||||
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x400000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_SYS_MMC_ENV_DEV=0
|
||||
|
||||
CONFIG_ULP_WATCHDOG=y
|
||||
CONFIG_SPL_WATCHDOG=y
|
||||
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_NXP_FSPI=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SF_DEFAULT_BUS=0
|
||||
CONFIG_SF_DEFAULT_CS=0
|
||||
CONFIG_SF_DEFAULT_SPEED=40000000
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
|
||||
CONFIG_IMX_RGPIO2P=y
|
||||
CONFIG_USE_ARCH_MEMCPY=y
|
||||
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_CMD_NET=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
|
||||
CONFIG_EFI_PARTITION=y
|
||||
|
||||
CONFIG_DM_PCA953X=y
|
||||
107
include/configs/imx8ulp_evk.h
Normal file
107
include/configs/imx8ulp_evk.h
Normal file
|
|
@ -0,0 +1,107 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2020 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8ULP_EVK_H
|
||||
#define __IMX8ULP_EVK_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN (SZ_64M)
|
||||
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
|
||||
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||
#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x22050000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x22048000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x22040000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x8000 /* 32 KB */
|
||||
|
||||
#define CONFIG_MALLOC_F_ADDR 0x22040000
|
||||
|
||||
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x95000000 /* SPL_RAM needed */
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_SERIAL_TAG
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_LATE_INIT
|
||||
|
||||
/* ENET Config */
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#define PHY_ANEG_TIMEOUT 20000
|
||||
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 1
|
||||
|
||||
#define IMX_FEC_BASE 0x29950000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISTRO_DEFAULTS
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(MMC, mmc, 0)
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
#else
|
||||
#define BOOTENV
|
||||
#endif
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
BOOTENV \
|
||||
"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
|
||||
"image=Image\0" \
|
||||
"console=ttyLP1,115200 earlycon\0" \
|
||||
"fdt_addr_r=0x83000000\0" \
|
||||
"boot_fit=no\0" \
|
||||
"fdtfile=imx8ulp-evk.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x80480000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_16M)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define PHYS_SDRAM 0x80000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Using ULP WDOG for reset */
|
||||
#define WDOG_BASE_ADDR WDG3_RBASE
|
||||
#endif
|
||||
Loading…
Reference in a new issue