2018-05-06 21:58:06 +00:00
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# SPDX-License-Identifier: GPL-2.0+
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2008-01-17 03:37:35 +00:00
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#
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# (C) Copyright 2000-2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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2013-03-11 06:08:00 +00:00
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# There are many options which enable SPI, so make this library available
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2020-06-04 15:11:53 +00:00
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ifdef CONFIG_$(SPL_TPL_)DM_SPI
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2014-10-14 05:41:52 +00:00
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obj-y += spi-uclass.o
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2020-06-16 23:06:31 +00:00
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obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
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2022-05-12 10:05:32 +00:00
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obj-$(CONFIG_CADENCE_OSPI_VERSAL) += cadence_ospi_versal.o
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2014-10-14 05:41:53 +00:00
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obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
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2014-10-14 05:42:00 +00:00
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obj-$(CONFIG_SOFT_SPI) += soft_spi.o
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spi: aspeed: Add ASPEED SPI controller driver
Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed-smc.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
2022-08-19 09:01:04 +00:00
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obj-$(CONFIG_SPI_ASPEED_SMC) += spi-aspeed-smc.o
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2018-08-16 15:30:11 +00:00
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obj-$(CONFIG_SPI_MEM) += spi-mem.o
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2019-04-16 16:01:59 +00:00
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obj-$(CONFIG_TI_QSPI) += ti_qspi.o
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2021-06-07 12:36:42 +00:00
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obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
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2014-10-14 05:41:52 +00:00
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else
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2013-10-17 08:34:57 +00:00
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obj-y += spi.o
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2019-02-05 05:59:15 +00:00
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obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
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2014-10-14 05:41:52 +00:00
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endif
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
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2022-01-23 15:48:12 +00:00
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obj-$(CONFIG_APPLE_SPI) += apple_spi.o
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2016-03-16 08:59:58 +00:00
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obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
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2019-06-18 08:51:50 +00:00
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obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
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2018-01-20 01:13:38 +00:00
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obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
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2023-06-07 23:37:05 +00:00
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obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o
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2018-01-23 16:14:58 +00:00
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obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
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2018-06-08 21:59:45 +00:00
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obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_CF_SPI) += cf_spi.o
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2020-07-30 19:52:45 +00:00
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obj-$(CONFIG_CORTINA_SFLASH) += ca_sflash.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
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2014-11-07 12:50:31 +00:00
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obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
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2015-06-27 08:21:53 +00:00
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obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
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obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
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2021-06-04 09:44:27 +00:00
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obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
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2022-06-08 21:21:36 +00:00
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obj-$(CONFIG_GXP_SPI) += gxp_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_ICH_SPI) += ich.o
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2022-02-09 22:16:13 +00:00
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obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
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2018-11-22 10:01:05 +00:00
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obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
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2022-10-27 06:02:01 +00:00
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obj-$(CONFIG_MICROCHIP_COREQSPI) += microchip_coreqspi.o
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2017-07-06 08:33:25 +00:00
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obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
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2019-07-22 11:39:01 +00:00
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obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
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2021-01-20 07:31:33 +00:00
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obj-$(CONFIG_MTK_SNOR) += mtk_snor.o
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2022-09-09 11:59:45 +00:00
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obj-$(CONFIG_MTK_SPIM) += mtk_spim.o
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2020-11-12 08:36:42 +00:00
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obj-$(CONFIG_MT7620_SPI) += mt7620_spi.o
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2018-08-16 08:48:48 +00:00
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obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
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2019-01-08 09:38:33 +00:00
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obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
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2016-05-19 13:56:44 +00:00
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obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_MXC_SPI) += mxc_spi.o
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obj-$(CONFIG_MXS_SPI) += mxs_spi.o
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2022-04-26 08:52:45 +00:00
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obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
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2022-05-31 10:14:02 +00:00
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obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o
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2019-12-17 23:09:58 +00:00
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obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
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2017-11-23 06:19:36 +00:00
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obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
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2020-07-30 11:56:18 +00:00
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obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
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2016-06-02 08:56:08 +00:00
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obj-$(CONFIG_PIC32_SPI) += pic32_spi.o
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2018-08-31 14:28:29 +00:00
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obj-$(CONFIG_PL022_SPI) += pl022_spi.o
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2020-10-08 20:05:09 +00:00
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obj-$(CONFIG_SPI_QUP) += spi-qup.o
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2021-06-23 17:15:15 +00:00
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obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
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2017-11-29 05:29:46 +00:00
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obj-$(CONFIG_RENESAS_RPC_SPI) += renesas_rpc_spi.o
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2021-08-05 08:26:38 +00:00
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obj-$(CONFIG_ROCKCHIP_SFC) += rockchip_sfc.o
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2015-09-02 01:19:37 +00:00
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obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
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2013-12-03 23:43:26 +00:00
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obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
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2019-07-17 04:23:43 +00:00
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obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
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2022-11-29 02:17:09 +00:00
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obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o
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2019-02-27 14:32:13 +00:00
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obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
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2013-12-18 06:31:55 +00:00
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obj-$(CONFIG_SH_QSPI) += sh_qspi.o
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2017-01-22 15:04:30 +00:00
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obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
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2019-04-30 16:08:28 +00:00
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obj-$(CONFIG_STM32_SPI) += stm32_spi.o
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2015-06-27 08:21:53 +00:00
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obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
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2015-10-12 21:50:54 +00:00
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obj-$(CONFIG_TEGRA210_QSPI) += tegra210_qspi.o
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2019-07-05 01:03:18 +00:00
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obj-$(CONFIG_UNIPHIER_SPI) += uniphier_spi.o
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2013-10-17 08:34:57 +00:00
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obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
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obj-$(CONFIG_ZYNQ_SPI) += zynq_spi.o
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2015-08-17 13:08:06 +00:00
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obj-$(CONFIG_ZYNQ_QSPI) += zynq_qspi.o
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2018-07-04 12:01:23 +00:00
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obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o
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