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https://github.com/AsahiLinux/u-boot
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spi: stm32: Add Serial Peripheral Interface driver for STM32MP
Add SPI driver support for STM32MP SoCs family. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
This commit is contained in:
Patrice Chotard
parent
248278d7f7
commit
a2a89b2e21
4 changed files with 625 additions and 0 deletions
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@ -312,6 +312,7 @@ F: drivers/ram/stm32mp1/
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F: drivers/misc/stm32_rcc.c
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F: drivers/reset/stm32-reset.c
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F: drivers/spi/stm32_qspi.c
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F: drivers/spi/stm32_spi.c
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F: drivers/watchdog/stm32mp_wdt.c
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ARM STM STV0991
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@ -234,6 +234,14 @@ config STM32_QSPI
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used to access the SPI NOR flash chips on platforms embedding
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this ST IP core.
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config STM32_SPI
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bool "STM32 SPI driver"
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depends on ARCH_STM32MP
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help
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Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP
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SoCs. This uses driver model and requires a device tree binding to
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operate.
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config TEGRA114_SPI
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bool "nVidia Tegra114 SPI driver"
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help
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@ -53,6 +53,7 @@ obj-$(CONFIG_SPI_SUNXI) += spi-sunxi.o
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obj-$(CONFIG_SH_SPI) += sh_spi.o
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obj-$(CONFIG_SH_QSPI) += sh_qspi.o
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obj-$(CONFIG_STM32_QSPI) += stm32_qspi.o
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obj-$(CONFIG_STM32_SPI) += stm32_spi.o
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obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
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obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
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obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
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615
drivers/spi/stm32_spi.c
Normal file
615
drivers/spi/stm32_spi.c
Normal file
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@ -0,0 +1,615 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
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*
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* Driver for STMicroelectronics Serial peripheral interface (SPI)
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <reset.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/bitfield.h>
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#include <linux/iopoll.h>
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/* STM32 SPI registers */
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#define STM32_SPI_CR1 0x00
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#define STM32_SPI_CR2 0x04
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#define STM32_SPI_CFG1 0x08
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#define STM32_SPI_CFG2 0x0C
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#define STM32_SPI_SR 0x14
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#define STM32_SPI_IFCR 0x18
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#define STM32_SPI_TXDR 0x20
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#define STM32_SPI_RXDR 0x30
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#define STM32_SPI_I2SCFGR 0x50
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/* STM32_SPI_CR1 bit fields */
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#define SPI_CR1_SPE BIT(0)
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#define SPI_CR1_MASRX BIT(8)
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#define SPI_CR1_CSTART BIT(9)
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#define SPI_CR1_CSUSP BIT(10)
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#define SPI_CR1_HDDIR BIT(11)
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#define SPI_CR1_SSI BIT(12)
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/* STM32_SPI_CR2 bit fields */
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#define SPI_CR2_TSIZE GENMASK(15, 0)
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/* STM32_SPI_CFG1 bit fields */
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#define SPI_CFG1_DSIZE GENMASK(4, 0)
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#define SPI_CFG1_DSIZE_MIN 3
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#define SPI_CFG1_FTHLV_SHIFT 5
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#define SPI_CFG1_FTHLV GENMASK(8, 5)
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#define SPI_CFG1_MBR_SHIFT 28
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#define SPI_CFG1_MBR GENMASK(30, 28)
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#define SPI_CFG1_MBR_MIN 0
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#define SPI_CFG1_MBR_MAX FIELD_GET(SPI_CFG1_MBR, SPI_CFG1_MBR)
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/* STM32_SPI_CFG2 bit fields */
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#define SPI_CFG2_COMM_SHIFT 17
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#define SPI_CFG2_COMM GENMASK(18, 17)
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#define SPI_CFG2_MASTER BIT(22)
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#define SPI_CFG2_LSBFRST BIT(23)
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#define SPI_CFG2_CPHA BIT(24)
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#define SPI_CFG2_CPOL BIT(25)
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#define SPI_CFG2_SSM BIT(26)
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#define SPI_CFG2_AFCNTR BIT(31)
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/* STM32_SPI_SR bit fields */
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#define SPI_SR_RXP BIT(0)
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#define SPI_SR_TXP BIT(1)
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#define SPI_SR_EOT BIT(3)
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#define SPI_SR_TXTF BIT(4)
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#define SPI_SR_OVR BIT(6)
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#define SPI_SR_SUSP BIT(11)
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#define SPI_SR_RXPLVL_SHIFT 13
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#define SPI_SR_RXPLVL GENMASK(14, 13)
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#define SPI_SR_RXWNE BIT(15)
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/* STM32_SPI_IFCR bit fields */
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#define SPI_IFCR_ALL GENMASK(11, 3)
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/* STM32_SPI_I2SCFGR bit fields */
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#define SPI_I2SCFGR_I2SMOD BIT(0)
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#define MAX_CS_COUNT 4
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/* SPI Master Baud Rate min/max divisor */
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#define STM32_MBR_DIV_MIN (2 << SPI_CFG1_MBR_MIN)
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#define STM32_MBR_DIV_MAX (2 << SPI_CFG1_MBR_MAX)
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#define STM32_SPI_TIMEOUT_US 100000
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/* SPI Communication mode */
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#define SPI_FULL_DUPLEX 0
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#define SPI_SIMPLEX_TX 1
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#define SPI_SIMPLEX_RX 2
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#define SPI_HALF_DUPLEX 3
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struct stm32_spi_priv {
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void __iomem *base;
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struct clk clk;
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struct reset_ctl rst_ctl;
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struct gpio_desc cs_gpios[MAX_CS_COUNT];
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ulong bus_clk_rate;
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unsigned int fifo_size;
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unsigned int cur_bpw;
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unsigned int cur_hz;
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unsigned int cur_xferlen; /* current transfer length in bytes */
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int tx_len; /* number of data to be written in bytes */
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int rx_len; /* number of data to be read in bytes */
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const void *tx_buf; /* data to be written, or NULL */
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void *rx_buf; /* data to be read, or NULL */
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u32 cur_mode;
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bool cs_high;
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};
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static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv)
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{
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while ((priv->tx_len > 0) &&
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(readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) {
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u32 offs = priv->cur_xferlen - priv->tx_len;
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if (priv->tx_len >= sizeof(u32) &&
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IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) {
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const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs);
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writel(*tx_buf32, priv->base + STM32_SPI_TXDR);
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priv->tx_len -= sizeof(u32);
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} else if (priv->tx_len >= sizeof(u16) &&
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IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) {
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const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs);
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writew(*tx_buf16, priv->base + STM32_SPI_TXDR);
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priv->tx_len -= sizeof(u16);
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} else {
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const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs);
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writeb(*tx_buf8, priv->base + STM32_SPI_TXDR);
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priv->tx_len -= sizeof(u8);
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}
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}
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debug("%s: %d bytes left\n", __func__, priv->tx_len);
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}
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static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv)
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{
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u32 sr = readl(priv->base + STM32_SPI_SR);
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u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
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while ((priv->rx_len > 0) &&
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((sr & SPI_SR_RXP) ||
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((sr & SPI_SR_EOT) && ((sr & SPI_SR_RXWNE) || (rxplvl > 0))))) {
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u32 offs = priv->cur_xferlen - priv->rx_len;
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if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u32)) &&
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(priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) {
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u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs);
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*rx_buf32 = readl(priv->base + STM32_SPI_RXDR);
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priv->rx_len -= sizeof(u32);
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} else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) &&
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(priv->rx_len >= sizeof(u16) ||
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(!(sr & SPI_SR_RXWNE) &&
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(rxplvl >= 2 || priv->cur_bpw > 8)))) {
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u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs);
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*rx_buf16 = readw(priv->base + STM32_SPI_RXDR);
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priv->rx_len -= sizeof(u16);
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} else {
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u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs);
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*rx_buf8 = readb(priv->base + STM32_SPI_RXDR);
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priv->rx_len -= sizeof(u8);
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}
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sr = readl(priv->base + STM32_SPI_SR);
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rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT;
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}
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debug("%s: %d bytes left\n", __func__, priv->rx_len);
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}
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static int stm32_spi_enable(struct stm32_spi_priv *priv)
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{
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debug("%s\n", __func__);
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/* Enable the SPI hardware */
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setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
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return 0;
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}
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static int stm32_spi_disable(struct stm32_spi_priv *priv)
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{
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debug("%s\n", __func__);
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/* Disable the SPI hardware */
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clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE);
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return 0;
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}
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static int stm32_spi_claim_bus(struct udevice *slave)
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{
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struct udevice *bus = dev_get_parent(slave);
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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debug("%s\n", __func__);
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/* Enable the SPI hardware */
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return stm32_spi_enable(priv);
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}
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static int stm32_spi_release_bus(struct udevice *slave)
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{
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struct udevice *bus = dev_get_parent(slave);
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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debug("%s\n", __func__);
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/* Disable the SPI hardware */
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return stm32_spi_disable(priv);
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}
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static void stm32_spi_stopxfer(struct udevice *dev)
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{
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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u32 cr1, sr;
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int ret;
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debug("%s\n", __func__);
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cr1 = readl(priv->base + STM32_SPI_CR1);
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if (!(cr1 & SPI_CR1_SPE))
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return;
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/* Wait on EOT or suspend the flow */
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ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr,
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!(sr & SPI_SR_EOT), 100000);
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if (ret < 0) {
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if (cr1 & SPI_CR1_CSTART) {
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writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1);
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if (readl_poll_timeout(priv->base + STM32_SPI_SR,
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sr, !(sr & SPI_SR_SUSP),
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100000) < 0)
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dev_err(dev, "Suspend request timeout\n");
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}
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}
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/* clear status flags */
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setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
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}
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static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable)
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{
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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debug("%s: cs=%d enable=%d\n", __func__, cs, enable);
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if (cs >= MAX_CS_COUNT)
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return -ENODEV;
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if (!dm_gpio_is_valid(&priv->cs_gpios[cs]))
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return -EINVAL;
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if (priv->cs_high)
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enable = !enable;
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return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0);
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}
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static int stm32_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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u32 cfg2_clrb = 0, cfg2_setb = 0;
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debug("%s: mode=%d\n", __func__, mode);
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if (mode & SPI_CPOL)
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cfg2_setb |= SPI_CFG2_CPOL;
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else
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cfg2_clrb |= SPI_CFG2_CPOL;
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if (mode & SPI_CPHA)
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cfg2_setb |= SPI_CFG2_CPHA;
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else
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cfg2_clrb |= SPI_CFG2_CPHA;
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if (mode & SPI_LSB_FIRST)
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cfg2_setb |= SPI_CFG2_LSBFRST;
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else
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cfg2_clrb |= SPI_CFG2_LSBFRST;
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if (cfg2_clrb || cfg2_setb)
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clrsetbits_le32(priv->base + STM32_SPI_CFG2,
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cfg2_clrb, cfg2_setb);
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if (mode & SPI_CS_HIGH)
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priv->cs_high = true;
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else
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priv->cs_high = false;
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return 0;
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}
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static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len)
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{
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struct stm32_spi_priv *priv = dev_get_priv(dev);
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u32 fthlv, half_fifo;
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/* data packet should not exceed 1/2 of fifo space */
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half_fifo = (priv->fifo_size / 2);
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/* data_packet should not exceed transfer length */
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fthlv = (half_fifo > xfer_len) ? xfer_len : half_fifo;
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/* align packet size with data registers access */
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fthlv -= (fthlv % 4);
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if (!fthlv)
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fthlv = 1;
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clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV,
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(fthlv - 1) << SPI_CFG1_FTHLV_SHIFT);
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return 0;
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}
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static int stm32_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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u32 div, mbrdiv;
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debug("%s: hz=%d\n", __func__, hz);
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if (priv->cur_hz == hz)
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return 0;
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div = DIV_ROUND_UP(priv->bus_clk_rate, hz);
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if (div < STM32_MBR_DIV_MIN ||
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div > STM32_MBR_DIV_MAX)
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return -EINVAL;
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/* Determine the first power of 2 greater than or equal to div */
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if (div & (div - 1))
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mbrdiv = fls(div);
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else
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mbrdiv = fls(div) - 1;
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if ((mbrdiv - 1) < 0)
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return -EINVAL;
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clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR,
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(mbrdiv - 1) << SPI_CFG1_MBR_SHIFT);
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priv->cur_hz = hz;
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return 0;
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}
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static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(slave);
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struct dm_spi_slave_platdata *slave_plat;
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struct stm32_spi_priv *priv = dev_get_priv(bus);
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u32 sr;
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u32 ifcr = 0;
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u32 xferlen;
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u32 mode;
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int xfer_status = 0;
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xferlen = bitlen / 8;
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if (xferlen <= SPI_CR2_TSIZE)
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writel(xferlen, priv->base + STM32_SPI_CR2);
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else
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return -EMSGSIZE;
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priv->tx_buf = dout;
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priv->rx_buf = din;
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priv->tx_len = priv->tx_buf ? bitlen / 8 : 0;
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priv->rx_len = priv->rx_buf ? bitlen / 8 : 0;
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mode = SPI_FULL_DUPLEX;
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if (!priv->tx_buf)
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mode = SPI_SIMPLEX_RX;
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else if (!priv->rx_buf)
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mode = SPI_SIMPLEX_TX;
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if (priv->cur_xferlen != xferlen || priv->cur_mode != mode) {
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priv->cur_mode = mode;
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priv->cur_xferlen = xferlen;
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/* Disable the SPI hardware to unlock CFG1/CFG2 registers */
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stm32_spi_disable(priv);
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clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM,
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mode << SPI_CFG2_COMM_SHIFT);
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stm32_spi_set_fthlv(bus, xferlen);
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/* Enable the SPI hardware */
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stm32_spi_enable(priv);
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}
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debug("%s: priv->tx_len=%d priv->rx_len=%d\n", __func__,
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||||
priv->tx_len, priv->rx_len);
|
||||
|
||||
slave_plat = dev_get_parent_platdata(slave);
|
||||
if (flags & SPI_XFER_BEGIN)
|
||||
stm32_spi_set_cs(bus, slave_plat->cs, false);
|
||||
|
||||
/* Be sure to have data in fifo before starting data transfer */
|
||||
if (priv->tx_buf)
|
||||
stm32_spi_write_txfifo(priv);
|
||||
|
||||
setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART);
|
||||
|
||||
while (1) {
|
||||
sr = readl(priv->base + STM32_SPI_SR);
|
||||
|
||||
if (sr & SPI_SR_OVR) {
|
||||
dev_err(bus, "Overrun: RX data lost\n");
|
||||
xfer_status = -EIO;
|
||||
break;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_SUSP) {
|
||||
dev_warn(bus, "System too slow is limiting data throughput\n");
|
||||
|
||||
if (priv->rx_buf && priv->rx_len > 0)
|
||||
stm32_spi_read_rxfifo(priv);
|
||||
|
||||
ifcr |= SPI_SR_SUSP;
|
||||
}
|
||||
|
||||
if (sr & SPI_SR_TXTF)
|
||||
ifcr |= SPI_SR_TXTF;
|
||||
|
||||
if (sr & SPI_SR_TXP)
|
||||
if (priv->tx_buf && priv->tx_len > 0)
|
||||
stm32_spi_write_txfifo(priv);
|
||||
|
||||
if (sr & SPI_SR_RXP)
|
||||
if (priv->rx_buf && priv->rx_len > 0)
|
||||
stm32_spi_read_rxfifo(priv);
|
||||
|
||||
if (sr & SPI_SR_EOT) {
|
||||
if (priv->rx_buf && priv->rx_len > 0)
|
||||
stm32_spi_read_rxfifo(priv);
|
||||
break;
|
||||
}
|
||||
|
||||
writel(ifcr, priv->base + STM32_SPI_IFCR);
|
||||
}
|
||||
|
||||
/* clear status flags */
|
||||
setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL);
|
||||
stm32_spi_stopxfer(bus);
|
||||
|
||||
if (flags & SPI_XFER_END)
|
||||
stm32_spi_set_cs(bus, slave_plat->cs, true);
|
||||
|
||||
return xfer_status;
|
||||
}
|
||||
|
||||
static int stm32_spi_get_fifo_size(struct udevice *dev)
|
||||
{
|
||||
struct stm32_spi_priv *priv = dev_get_priv(dev);
|
||||
u32 count = 0;
|
||||
|
||||
stm32_spi_enable(priv);
|
||||
|
||||
while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)
|
||||
writeb(++count, priv->base + STM32_SPI_TXDR);
|
||||
|
||||
stm32_spi_disable(priv);
|
||||
|
||||
debug("%s %d x 8-bit fifo size\n", __func__, count);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static int stm32_spi_probe(struct udevice *dev)
|
||||
{
|
||||
struct stm32_spi_priv *priv = dev_get_priv(dev);
|
||||
unsigned long clk_rate;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
priv->base = dev_remap_addr(dev);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
/* enable clock */
|
||||
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
clk_rate = clk_get_rate(&priv->clk);
|
||||
if (!clk_rate) {
|
||||
ret = -EINVAL;
|
||||
goto clk_err;
|
||||
}
|
||||
|
||||
priv->bus_clk_rate = clk_rate;
|
||||
|
||||
/* perform reset */
|
||||
ret = reset_get_by_index(dev, 0, &priv->rst_ctl);
|
||||
if (ret < 0)
|
||||
goto clk_err;
|
||||
|
||||
reset_assert(&priv->rst_ctl);
|
||||
udelay(2);
|
||||
reset_deassert(&priv->rst_ctl);
|
||||
|
||||
ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios,
|
||||
ARRAY_SIZE(priv->cs_gpios), 0);
|
||||
if (ret < 0) {
|
||||
pr_err("Can't get %s cs gpios: %d", dev->name, ret);
|
||||
goto reset_err;
|
||||
}
|
||||
|
||||
priv->fifo_size = stm32_spi_get_fifo_size(dev);
|
||||
|
||||
priv->cur_mode = SPI_FULL_DUPLEX;
|
||||
priv->cur_xferlen = 0;
|
||||
priv->cur_bpw = SPI_DEFAULT_WORDLEN;
|
||||
clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE,
|
||||
priv->cur_bpw - 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) {
|
||||
if (!dm_gpio_is_valid(&priv->cs_gpios[i]))
|
||||
continue;
|
||||
|
||||
dm_gpio_set_dir_flags(&priv->cs_gpios[i],
|
||||
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
|
||||
}
|
||||
|
||||
/* Ensure I2SMOD bit is kept cleared */
|
||||
clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD);
|
||||
|
||||
/*
|
||||
* - SS input value high
|
||||
* - transmitter half duplex direction
|
||||
* - automatic communication suspend when RX-Fifo is full
|
||||
*/
|
||||
setbits_le32(priv->base + STM32_SPI_CR1,
|
||||
SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX);
|
||||
|
||||
/*
|
||||
* - Set the master mode (default Motorola mode)
|
||||
* - Consider 1 master/n slaves configuration and
|
||||
* SS input value is determined by the SSI bit
|
||||
* - keep control of all associated GPIOs
|
||||
*/
|
||||
setbits_le32(priv->base + STM32_SPI_CFG2,
|
||||
SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR);
|
||||
|
||||
return 0;
|
||||
|
||||
reset_err:
|
||||
reset_free(&priv->rst_ctl);
|
||||
|
||||
clk_err:
|
||||
clk_disable(&priv->clk);
|
||||
clk_free(&priv->clk);
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
static int stm32_spi_remove(struct udevice *dev)
|
||||
{
|
||||
struct stm32_spi_priv *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
stm32_spi_stopxfer(dev);
|
||||
stm32_spi_disable(priv);
|
||||
|
||||
ret = reset_assert(&priv->rst_ctl);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
reset_free(&priv->rst_ctl);
|
||||
|
||||
ret = clk_disable(&priv->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
clk_free(&priv->clk);
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
static const struct dm_spi_ops stm32_spi_ops = {
|
||||
.claim_bus = stm32_spi_claim_bus,
|
||||
.release_bus = stm32_spi_release_bus,
|
||||
.set_mode = stm32_spi_set_mode,
|
||||
.set_speed = stm32_spi_set_speed,
|
||||
.xfer = stm32_spi_xfer,
|
||||
};
|
||||
|
||||
static const struct udevice_id stm32_spi_ids[] = {
|
||||
{ .compatible = "st,stm32h7-spi", },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(stm32_spi) = {
|
||||
.name = "stm32_spi",
|
||||
.id = UCLASS_SPI,
|
||||
.of_match = stm32_spi_ids,
|
||||
.ops = &stm32_spi_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct stm32_spi_priv),
|
||||
.probe = stm32_spi_probe,
|
||||
.remove = stm32_spi_remove,
|
||||
};
|
||||
Loading…
Reference in a new issue