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spi: npcm-fiu: add NPCM7xx FIU controller driver
Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. The FIU controller driver provides flash access in UMA(User Mode Access) mode by using an indirect address/data mechanism. the dts node is followed upstream kernel dts name. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [Jagan: fixed the Kconfig, Makefile order] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jim Liu
Jagan Teki
parent
f9b9641348
commit
aaf2dbc82b
3 changed files with 394 additions and 0 deletions
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@ -283,6 +283,12 @@ config SPI_MXIC
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can be used to access the SPI flash on platforms embedding
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this Macronix IP core.
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config NPCM_FIU_SPI
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bool "FIU driver for Nuvoton NPCM SoC"
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help
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This enables support for the Flash Interface Unit SPI controller
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in master mode.
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config NXP_FSPI
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bool "NXP FlexSPI driver"
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depends on SPI_MEM
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@ -47,6 +47,7 @@ obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
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obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
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obj-$(CONFIG_MXC_SPI) += mxc_spi.o
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obj-$(CONFIG_MXS_SPI) += mxs_spi.o
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obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o
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obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o
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obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o
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obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o
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387
drivers/spi/npcm_fiu_spi.c
Normal file
387
drivers/spi/npcm_fiu_spi.c
Normal file
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@ -0,0 +1,387 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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* NPCM Flash Interface Unit(FIU) SPI master controller driver.
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*/
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#include <clk.h>
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#include <dm.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <linux/bitfield.h>
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#include <linux/log2.h>
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#include <linux/iopoll.h>
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#define DW_SIZE 4
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#define CHUNK_SIZE 16
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#define XFER_TIMEOUT 1000000
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/* FIU UMA Configuration Register (UMA_CFG) */
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#define UMA_CFG_RDATSIZ_MASK GENMASK(28, 24)
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#define UMA_CFG_DBSIZ_MASK GENMASK(23, 21)
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#define UMA_CFG_WDATSIZ_MASK GENMASK(20, 16)
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#define UMA_CFG_ADDSIZ_MASK GENMASK(13, 11)
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#define UMA_CFG_RDBPCK_MASK GENMASK(9, 8)
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#define UMA_CFG_DBPCK_MASK GENMASK(7, 6)
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#define UMA_CFG_WDBPCK_MASK GENMASK(5, 4)
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#define UMA_CFG_ADBPCK_MASK GENMASK(3, 2)
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#define UMA_CFG_CMBPCK_MASK GENMASK(1, 0)
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#define UMA_CFG_CMDSIZ_SHIFT 10
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/* FIU UMA Control and Status Register (UMA_CTS) */
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#define UMA_CTS_SW_CS BIT(16)
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#define UMA_CTS_EXEC_DONE BIT(0)
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#define UMA_CTS_RDYST BIT(24)
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#define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8)
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struct npcm_fiu_regs {
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unsigned int drd_cfg;
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unsigned int dwr_cfg;
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unsigned int uma_cfg;
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unsigned int uma_cts;
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unsigned int uma_cmd;
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unsigned int uma_addr;
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unsigned int prt_cfg;
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unsigned char res1[4];
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unsigned int uma_dw0;
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unsigned int uma_dw1;
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unsigned int uma_dw2;
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unsigned int uma_dw3;
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unsigned int uma_dr0;
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unsigned int uma_dr1;
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unsigned int uma_dr2;
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unsigned int uma_dr3;
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unsigned int prt_cmd0;
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unsigned int prt_cmd1;
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unsigned int prt_cmd2;
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unsigned int prt_cmd3;
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unsigned int prt_cmd4;
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unsigned int prt_cmd5;
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unsigned int prt_cmd6;
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unsigned int prt_cmd7;
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unsigned int prt_cmd8;
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unsigned int prt_cmd9;
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unsigned int stuff[4];
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unsigned int fiu_cfg;
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};
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struct npcm_fiu_priv {
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struct npcm_fiu_regs *regs;
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struct clk clk;
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};
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static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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int ret;
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debug("%s: set speed %u\n", bus->name, speed);
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ret = clk_set_rate(&priv->clk, speed);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int npcm_fiu_spi_set_mode(struct udevice *bus, uint mode)
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{
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return 0;
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}
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static inline void activate_cs(struct npcm_fiu_regs *regs, int cs)
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{
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writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs), ®s->uma_cts);
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}
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static inline void deactivate_cs(struct npcm_fiu_regs *regs, int cs)
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{
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writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs) | UMA_CTS_SW_CS, ®s->uma_cts);
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}
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static int fiu_uma_read(struct udevice *bus, u8 *buf, u32 size)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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struct npcm_fiu_regs *regs = priv->regs;
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u32 data_reg[4];
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u32 val;
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int ret;
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/* Set data size */
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writel(FIELD_PREP(UMA_CFG_RDATSIZ_MASK, size), ®s->uma_cfg);
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/* Initiate the read */
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writel(readl(®s->uma_cts) | UMA_CTS_EXEC_DONE, ®s->uma_cts);
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/* Wait for completion */
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ret = readl_poll_timeout(®s->uma_cts, val,
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!(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT);
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if (ret) {
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printf("npcm_fiu: read timeout\n");
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return ret;
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}
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/* Copy data from data registers */
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if (size)
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data_reg[0] = readl(®s->uma_dr0);
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if (size > DW_SIZE)
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data_reg[1] = readl(®s->uma_dr1);
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if (size > DW_SIZE * 2)
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data_reg[2] = readl(®s->uma_dr2);
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if (size > DW_SIZE * 3)
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data_reg[3] = readl(®s->uma_dr3);
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memcpy(buf, data_reg, size);
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return 0;
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}
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static int fiu_uma_write(struct udevice *bus, const u8 *buf, u32 size)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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struct npcm_fiu_regs *regs = priv->regs;
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u32 data_reg[4];
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u32 val;
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int ret;
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/* Set data size */
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writel(FIELD_PREP(UMA_CFG_WDATSIZ_MASK, size), ®s->uma_cfg);
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/* Write data to data registers */
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memcpy(data_reg, buf, size);
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if (size)
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writel(data_reg[0], ®s->uma_dw0);
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if (size > DW_SIZE)
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writel(data_reg[1], ®s->uma_dw1);
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if (size > DW_SIZE * 2)
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writel(data_reg[2], ®s->uma_dw2);
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if (size > DW_SIZE * 3)
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writel(data_reg[3], ®s->uma_dw3);
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/* Initiate the transaction */
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writel(readl(®s->uma_cts) | UMA_CTS_EXEC_DONE, ®s->uma_cts);
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/* Wait for completion */
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ret = readl_poll_timeout(®s->uma_cts, val,
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!(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT);
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if (ret)
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printf("npcm_fiu: write timeout\n");
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return ret;
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}
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static int npcm_fiu_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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struct npcm_fiu_regs *regs = priv->regs;
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struct dm_spi_slave_plat *slave_plat =
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dev_get_parent_plat(dev);
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const u8 *tx = dout;
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u8 *rx = din;
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int bytes = bitlen / 8;
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int ret = 0;
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int len;
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if (flags & SPI_XFER_BEGIN)
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activate_cs(regs, slave_plat->cs);
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while (bytes) {
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len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes;
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if (tx) {
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ret = fiu_uma_write(bus, tx, len);
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if (ret)
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break;
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tx += len;
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} else {
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ret = fiu_uma_read(bus, rx, len);
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if (ret)
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break;
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rx += len;
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}
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bytes -= len;
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}
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if (flags & SPI_XFER_END)
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deactivate_cs(regs, slave_plat->cs);
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return ret;
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}
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static int npcm_fiu_uma_operation(struct npcm_fiu_priv *priv, const struct spi_mem_op *op,
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u32 addr, const u8 *tx, u8 *rx, u32 nbytes, bool started)
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{
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struct npcm_fiu_regs *regs = priv->regs;
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u32 uma_cfg = 0, val;
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u32 data_reg[4];
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int ret;
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debug("fiu_uma: opcode 0x%x, dir %d, addr 0x%x, %d bytes\n",
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op->cmd.opcode, op->data.dir, addr, nbytes);
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debug(" buswidth cmd:%d, addr:%d, dummy:%d, data:%d\n",
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op->cmd.buswidth, op->addr.buswidth, op->dummy.buswidth,
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op->data.buswidth);
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debug(" size cmd:%d, addr:%d, dummy:%d, data:%d\n",
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1, op->addr.nbytes, op->dummy.nbytes, op->data.nbytes);
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debug(" tx %p, rx %p\n", tx, rx);
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if (!started) {
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/* Send cmd/addr in the begin of an transaction */
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writel(op->cmd.opcode, ®s->uma_cmd);
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uma_cfg |= FIELD_PREP(UMA_CFG_CMBPCK_MASK, ilog2(op->cmd.buswidth)) |
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(1 << UMA_CFG_CMDSIZ_SHIFT);
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/* Configure addr bytes */
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if (op->addr.nbytes) {
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uma_cfg |= FIELD_PREP(UMA_CFG_ADBPCK_MASK, ilog2(op->addr.buswidth)) |
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FIELD_PREP(UMA_CFG_ADDSIZ_MASK, op->addr.nbytes);
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writel(addr, ®s->uma_addr);
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}
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/* Configure dummy bytes */
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if (op->dummy.nbytes)
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uma_cfg |= FIELD_PREP(UMA_CFG_DBPCK_MASK, ilog2(op->dummy.buswidth)) |
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FIELD_PREP(UMA_CFG_DBSIZ_MASK, op->dummy.nbytes);
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}
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/* Set data bus width and data size */
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if (op->data.dir == SPI_MEM_DATA_IN && nbytes)
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uma_cfg |= FIELD_PREP(UMA_CFG_RDBPCK_MASK, ilog2(op->data.buswidth)) |
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FIELD_PREP(UMA_CFG_RDATSIZ_MASK, nbytes);
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else if (op->data.dir == SPI_MEM_DATA_OUT && nbytes)
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uma_cfg |= FIELD_PREP(UMA_CFG_WDBPCK_MASK, ilog2(op->data.buswidth)) |
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FIELD_PREP(UMA_CFG_WDATSIZ_MASK, nbytes);
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writel(uma_cfg, ®s->uma_cfg);
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if (op->data.dir == SPI_MEM_DATA_OUT && nbytes) {
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memcpy(data_reg, tx, nbytes);
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if (nbytes)
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writel(data_reg[0], ®s->uma_dw0);
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if (nbytes > DW_SIZE)
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writel(data_reg[1], ®s->uma_dw1);
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if (nbytes > DW_SIZE * 2)
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writel(data_reg[2], ®s->uma_dw2);
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if (nbytes > DW_SIZE * 3)
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writel(data_reg[3], ®s->uma_dw3);
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}
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/* Initiate the transaction */
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writel(readl(®s->uma_cts) | UMA_CTS_EXEC_DONE, ®s->uma_cts);
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/* Wait for completion */
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ret = readl_poll_timeout(®s->uma_cts, val,
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!(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT);
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if (ret) {
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printf("npcm_fiu: UMA op timeout\n");
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return ret;
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}
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if (op->data.dir == SPI_MEM_DATA_IN && nbytes) {
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if (nbytes)
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data_reg[0] = readl(®s->uma_dr0);
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if (nbytes > DW_SIZE)
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data_reg[1] = readl(®s->uma_dr1);
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if (nbytes > DW_SIZE * 2)
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data_reg[2] = readl(®s->uma_dr2);
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if (nbytes > DW_SIZE * 3)
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data_reg[3] = readl(®s->uma_dr3);
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memcpy(rx, data_reg, nbytes);
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}
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return 0;
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}
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static int npcm_fiu_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = slave->dev->parent;
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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struct npcm_fiu_regs *regs = priv->regs;
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struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev);
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u32 bytes, len, addr;
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const u8 *tx;
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u8 *rx;
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bool started = false;
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int ret;
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bytes = op->data.nbytes;
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addr = (u32)op->addr.val;
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if (!bytes) {
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activate_cs(regs, slave_plat->cs);
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ret = npcm_fiu_uma_operation(priv, op, addr, NULL, NULL, 0, false);
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deactivate_cs(regs, slave_plat->cs);
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return ret;
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}
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tx = op->data.buf.out;
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rx = op->data.buf.in;
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/*
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* Use SW-control CS for write to extend the transaction and
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* keep the Write Enable state.
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* Use HW-control CS for read to avoid clock and timing issues.
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*/
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if (op->data.dir == SPI_MEM_DATA_OUT)
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activate_cs(regs, slave_plat->cs);
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else
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writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, slave_plat->cs) | UMA_CTS_SW_CS,
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®s->uma_cts);
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while (bytes) {
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len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes;
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ret = npcm_fiu_uma_operation(priv, op, addr, tx, rx, len, started);
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if (ret)
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return ret;
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/* CS is kept low for uma write, extend the transaction */
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if (op->data.dir == SPI_MEM_DATA_OUT)
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started = true;
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bytes -= len;
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addr += len;
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if (tx)
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tx += len;
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if (rx)
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rx += len;
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}
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if (op->data.dir == SPI_MEM_DATA_OUT)
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deactivate_cs(regs, slave_plat->cs);
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return 0;
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}
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static int npcm_fiu_spi_probe(struct udevice *bus)
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{
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struct npcm_fiu_priv *priv = dev_get_priv(bus);
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int ret;
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priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus);
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ret = clk_get_by_index(bus, 0, &priv->clk);
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if (ret < 0)
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return ret;
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return 0;
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}
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static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
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.exec_op = npcm_fiu_exec_op,
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};
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static const struct dm_spi_ops npcm_fiu_spi_ops = {
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.xfer = npcm_fiu_spi_xfer,
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.set_speed = npcm_fiu_spi_set_speed,
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.set_mode = npcm_fiu_spi_set_mode,
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.mem_ops = &npcm_fiu_mem_ops,
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};
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static const struct udevice_id npcm_fiu_spi_ids[] = {
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{ .compatible = "nuvoton,npcm845-fiu" },
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{ .compatible = "nuvoton,npcm750-fiu" },
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{ }
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};
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U_BOOT_DRIVER(npcm_fiu_spi) = {
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.name = "npcm_fiu_spi",
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.id = UCLASS_SPI,
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.of_match = npcm_fiu_spi_ids,
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.ops = &npcm_fiu_spi_ops,
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.priv_auto = sizeof(struct npcm_fiu_priv),
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.probe = npcm_fiu_spi_probe,
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};
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