2011-10-14 02:58:23 +00:00
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/*
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2013-03-15 10:07:04 +00:00
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* clock_am33xx.c
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2011-10-14 02:58:23 +00:00
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*
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* clocks for AM33XX based boards
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*
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2013-03-15 10:07:04 +00:00
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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2011-10-14 02:58:23 +00:00
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2011-10-14 02:58:23 +00:00
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#define PRCM_MOD_EN 0x2
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#define PRCM_FORCE_WAKEUP 0x2
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2012-07-24 12:22:17 +00:00
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#define PRCM_FUNCTL 0x0
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2011-10-14 02:58:23 +00:00
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2012-07-24 12:22:17 +00:00
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#define CPGMAC0_IDLE 0x30000
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2013-03-15 10:07:04 +00:00
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#define OSC (V_OSCK/1000000)
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2011-10-14 02:58:23 +00:00
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const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
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const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
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const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
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2012-03-08 11:45:47 +00:00
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const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
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2011-10-14 02:58:23 +00:00
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2013-07-30 05:18:52 +00:00
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const struct dpll_regs dpll_mpu_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x88,
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.cm_idlest_dpll = CM_WKUP + 0x20,
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.cm_clksel_dpll = CM_WKUP + 0x2C,
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.cm_div_m2_dpll = CM_WKUP + 0xA8,
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};
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const struct dpll_regs dpll_core_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x90,
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.cm_idlest_dpll = CM_WKUP + 0x5C,
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.cm_clksel_dpll = CM_WKUP + 0x68,
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.cm_div_m4_dpll = CM_WKUP + 0x80,
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.cm_div_m5_dpll = CM_WKUP + 0x84,
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.cm_div_m6_dpll = CM_WKUP + 0xD8,
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};
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const struct dpll_regs dpll_per_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x8C,
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.cm_idlest_dpll = CM_WKUP + 0x70,
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.cm_clksel_dpll = CM_WKUP + 0x9C,
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.cm_div_m2_dpll = CM_WKUP + 0xAC,
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};
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const struct dpll_regs dpll_ddr_regs = {
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.cm_clkmode_dpll = CM_WKUP + 0x94,
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.cm_idlest_dpll = CM_WKUP + 0x34,
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.cm_clksel_dpll = CM_WKUP + 0x40,
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.cm_div_m2_dpll = CM_WKUP + 0xA0,
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};
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const struct dpll_params dpll_mpu = {
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CONFIG_SYS_MPUCLK, OSC-1, 1, -1, -1, -1, -1};
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const struct dpll_params dpll_core = {
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1000, OSC-1, -1, -1, 10, 8, 4};
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const struct dpll_params dpll_per = {
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960, OSC-1, 5, -1, -1, -1, -1};
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2011-10-14 02:58:23 +00:00
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static void enable_interface_clocks(void)
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{
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/* Enable all the Interconnect Modules */
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writel(PRCM_MOD_EN, &cmper->l3clkctrl);
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while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
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while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
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while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
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while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
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while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
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while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
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2012-07-31 14:22:47 +00:00
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;
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writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
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while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
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2011-10-14 02:58:23 +00:00
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;
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}
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/*
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* Force power domain wake up transition
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* Ensure that the corresponding interface clock is active before
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* using the peripheral
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*/
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static void power_domain_wkup_transition(void)
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{
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writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
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writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
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}
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/*
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* Enable the peripheral clock for required peripherals
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*/
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static void enable_per_clocks(void)
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{
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/* Enable the control module though RBL would have done it*/
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writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
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while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
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;
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/* Enable the module clock */
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writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
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while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
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;
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2012-01-09 20:38:56 +00:00
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/* Select the Master osc 24 MHZ as Timer2 clock source */
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writel(0x1, &cmdpll->clktimer2clk);
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2011-10-14 02:58:23 +00:00
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/* UART0 */
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writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
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while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
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;
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2012-01-09 20:38:58 +00:00
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2012-10-25 12:21:29 +00:00
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/* UART1 */
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#ifdef CONFIG_SERIAL2
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writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
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while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
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;
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#endif /* CONFIG_SERIAL2 */
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/* UART2 */
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#ifdef CONFIG_SERIAL3
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writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
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while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
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;
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#endif /* CONFIG_SERIAL3 */
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/* UART3 */
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#ifdef CONFIG_SERIAL4
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writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
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while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
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;
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#endif /* CONFIG_SERIAL4 */
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/* UART4 */
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#ifdef CONFIG_SERIAL5
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writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
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while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
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;
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#endif /* CONFIG_SERIAL5 */
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/* UART5 */
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#ifdef CONFIG_SERIAL6
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writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
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while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
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;
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#endif /* CONFIG_SERIAL6 */
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2012-11-06 13:06:30 +00:00
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/* GPMC */
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writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
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while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
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;
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2012-11-06 13:06:32 +00:00
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/* ELM */
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writel(PRCM_MOD_EN, &cmper->elmclkctrl);
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while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
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;
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2012-01-09 20:38:58 +00:00
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/* MMC0*/
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writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
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while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
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;
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2012-01-22 23:47:01 +00:00
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2013-04-03 08:50:01 +00:00
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/* MMC1 */
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writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
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while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
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;
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2012-01-22 23:47:01 +00:00
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/* i2c0 */
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writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
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while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
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;
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2012-06-04 05:35:34 +00:00
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/* gpio1 module */
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writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
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while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
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;
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/* gpio2 module */
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writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
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while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
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;
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/* gpio3 module */
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writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
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while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
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;
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2012-06-22 07:45:57 +00:00
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/* i2c1 */
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writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
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while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
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;
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2012-07-24 12:22:17 +00:00
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/* Ethernet */
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writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
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while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
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;
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2012-08-08 21:29:51 +00:00
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/* spi0 */
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writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
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while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
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;
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2012-03-08 11:45:47 +00:00
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/* RTC */
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writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
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while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
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;
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2012-11-06 13:48:23 +00:00
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/* MUSB */
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writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
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while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
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;
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2011-10-14 02:58:23 +00:00
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}
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void enable_emif_clocks(void)
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{
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/* Enable the EMIF_FW Functional clock */
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writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
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/* Enable EMIF0 Clock */
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writel(PRCM_MOD_EN, &cmper->emifclkctrl);
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/* Poll if module is functional */
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while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
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;
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}
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/*
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* Configure the PLL/PRCM for necessary peripherals
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*/
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void pll_init()
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{
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2013-07-30 05:18:52 +00:00
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setup_dplls();
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2011-10-14 02:58:23 +00:00
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/* Enable the required interconnect clocks */
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enable_interface_clocks();
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/* Power domain wake up transition */
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power_domain_wkup_transition();
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/* Enable the required peripherals */
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enable_per_clocks();
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}
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