2015-10-09 20:58:28 +00:00
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if ARCH_RMOBILE
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2014-08-30 22:10:57 +00:00
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choice
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2016-06-17 04:52:13 +00:00
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prompt "Target Renesas SoC select"
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default RCAR_32
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2014-08-30 22:10:57 +00:00
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2016-06-17 04:52:13 +00:00
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config RCAR_32
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bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
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2018-04-26 12:51:26 +00:00
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select CPU_V7A
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2015-03-04 23:30:37 +00:00
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2016-03-31 18:51:34 +00:00
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config RCAR_GEN3
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bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
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select ARM64
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2018-10-02 20:48:26 +00:00
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select PHY
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2018-09-26 05:32:13 +00:00
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select CMD_CACHE
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2019-04-21 20:14:11 +00:00
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select PINCTRL
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select PINCONF
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select PINCTRL_PFC
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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select SUPPORT_SPL
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2018-12-03 22:46:11 +00:00
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imply CMD_FS_UUID
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imply CMD_GPT
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imply CMD_UUID
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imply CMD_MMC_SWRITE if MMC
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imply SUPPORT_EMMC_RPMB if MMC
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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imply SPL
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imply SPL_BOARD_INIT
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imply SPL_GZIP
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imply SPL_LIBCOMMON_SUPPORT
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imply SPL_LIBGENERIC_SUPPORT
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imply SPL_SERIAL_SUPPORT
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imply SPL_SYS_MALLOC_SIMPLE
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imply SPL_TINY_MEMSET
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imply SPL_YMODEM_SUPPORT
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2019-09-25 14:56:27 +00:00
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imply SPL_USE_TINY_PRINTF
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2016-03-31 18:51:34 +00:00
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2017-08-23 19:53:59 +00:00
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config RZA1
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prompt "Renesas ARM SoCs RZ/A1 (32bit)"
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select CPU_V7A
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2015-03-04 23:30:37 +00:00
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endchoice
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2016-06-17 04:52:13 +00:00
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source "arch/arm/mach-rmobile/Kconfig.32"
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2016-03-31 18:51:34 +00:00
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source "arch/arm/mach-rmobile/Kconfig.64"
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2017-08-23 19:53:59 +00:00
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source "arch/arm/mach-rmobile/Kconfig.rza1"
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2014-08-30 22:10:57 +00:00
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endif
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