Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-16 09:48:16 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/drivers/clk/sunxi/clk_h6.c

126 lines
3.7 KiB
C
Raw Normal View History

clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2018 Amarula Solutions.
* Author: Jagan Teki <jagan@amarulasolutions.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
clk: sunxi: Move header out of arch directory The CCU header is only used by the DM drivers, not any platform code. Its current location adds an artificial dependency on CONFIG_ARM and ARCH_SUNXI, which will be problematic when adding the CCU driver for a RISC-V sunxi platform. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 16:48:43 +00:00
#include <clk/sunxi.h>
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-10 17:40:13 +00:00
#include <linux/bitops.h>
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
static struct ccu_clk_gate h6_gates[] = {
clk: sunxi: add PIO bus gate clocks The introduction of the DM pinctrl driver made its probe function enable all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device. So far we didn't describe those clocks in our clock driver. As we enable them already in the SPL, the devices happen to work, but the clock driver still complains about not finding those clocks: ========= sunxi_set_gate: (CLK#58) unhandled ========= Add the one-liners that are needed to announce the gate bit for those clocks, to silence that message on the console. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-04 21:10:28 +00:00
[CLK_PLL_PERIPH0] = GATE(0x020, BIT(31)),
clk: sunxi: add and use dummy gate clocks Some devices enumerate various clocks in their DT, and many drivers just blanketly try to enable all of them. This creates problems since we only model a few gate clocks, and the clock driver outputs a warning when a clock is not described: ========= sunxi_set_gate: (CLK#3) unhandled ========= Some clocks don't have an enable bit, or are already enabled in a different way, so we might want to just ignore them. Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define a GATE_DUMMY macro that can be used in the clock description array. Define a few clocks, used by some pinctrl devices, that way to suppress the runtime warnings. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
2022-05-05 00:25:43 +00:00
[CLK_APB1] = GATE_DUMMY,
clk: sunxi: Add DE2 display-related clocks/resets Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-28 07:02:24 +00:00
[CLK_DE] = GATE(0x600, BIT(31)),
[CLK_BUS_DE] = GATE(0x60c, BIT(0)),
clk: sunxi: Add NAND clocks and resets Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-22 22:06:31 +00:00
[CLK_NAND0] = GATE(0x810, BIT(31)),
[CLK_NAND1] = GATE(0x814, BIT(31)),
[CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:09 +00:00
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
[CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
[CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
clk: sunxi: Add support for I2C gates/resets Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:24 +00:00
[CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
[CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
[CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
[CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
[CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
[CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
clk: sunxi: Implement EMAC, GMAC clocks, resets - Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27 18:56:57 +00:00
[CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
sunxi: clocks: Add H6 USB clock gates and resets To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-23 14:09:48 +00:00
[CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
[CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
[CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
[CLK_USB_HSIC] = GATE(0xa7c, BIT(26)),
[CLK_USB_HSIC_12M] = GATE(0xa7c, BIT(27)),
[CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
[CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
[CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
[CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
[CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
clk: sunxi: h6: Add XHCI clocks The XHCI controller has its own clock and reset. Add them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-08 05:57:20 +00:00
[CLK_BUS_XHCI] = GATE(0xa8c, BIT(5)),
sunxi: clocks: Add H6 USB clock gates and resets To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-23 14:09:48 +00:00
[CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
[CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
clk: sunxi: Add DE2 display-related clocks/resets Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-28 07:02:24 +00:00
[CLK_HDMI] = GATE(0xb00, BIT(31)),
[CLK_HDMI_SLOW] = GATE(0xb04, BIT(31)),
[CLK_HDMI_CEC] = GATE(0xb10, BIT(31)),
[CLK_BUS_HDMI] = GATE(0xb1c, BIT(0)),
[CLK_BUS_TCON_TOP] = GATE(0xb5c, BIT(0)),
[CLK_TCON_LCD0] = GATE(0xb60, BIT(31)),
[CLK_BUS_TCON_LCD0] = GATE(0xb7c, BIT(0)),
[CLK_TCON_TV0] = GATE(0xb80, BIT(31)),
[CLK_BUS_TCON_TV0] = GATE(0xb9c, BIT(0)),
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
};
static struct ccu_reset h6_resets[] = {
clk: sunxi: Add DE2 display-related clocks/resets Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-28 07:02:24 +00:00
[RST_BUS_DE] = RESET(0x60c, BIT(16)),
clk: sunxi: Add NAND clocks and resets Currently NAND clock setup is done in board code, both in SPL and in U-Boot proper. Add the NAND clocks/resets here so they can be used by the "full" NAND driver once it is converted to the driver model. The bit locations are copied from the Linux CCU drivers. Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Sean Anderson <seanga2@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-01-22 22:06:31 +00:00
[RST_BUS_NAND] = RESET(0x82c, BIT(16)),
clk: sunxi: Add DE2 display-related clocks/resets Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-28 07:02:24 +00:00
sunxi: clk: add MMC gates/resets Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 15:54:09 +00:00
[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
[RST_BUS_UART0] = RESET(0x90c, BIT(16)),
[RST_BUS_UART1] = RESET(0x90c, BIT(17)),
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
clk: sunxi: Add support for I2C gates/resets Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-09-12 14:47:24 +00:00
[RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
[RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
[RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
[RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
clk: sunxi: Implement SPI clocks, resets - Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-02-27 14:32:06 +00:00
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
clk: sunxi: Implement EMAC, GMAC clocks, resets - Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-27 18:56:57 +00:00
[RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
sunxi: clocks: Add H6 USB clock gates and resets To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-23 14:09:48 +00:00
[RST_USB_PHY0] = RESET(0xa70, BIT(30)),
[RST_USB_PHY1] = RESET(0xa74, BIT(30)),
[RST_USB_HSIC] = RESET(0xa7c, BIT(28)),
[RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
[RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
[RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
[RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
clk: sunxi: h6: Add XHCI clocks The XHCI controller has its own clock and reset. Add them. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-08 05:57:20 +00:00
[RST_BUS_XHCI] = RESET(0xa8c, BIT(21)),
sunxi: clocks: Add H6 USB clock gates and resets To enable USB support in U-Boot, add the required clock and reset gates to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will pick them up from there automatically. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64 Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-06-23 14:09:48 +00:00
[RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
clk: sunxi: Add DE2 display-related clocks/resets Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland <samuel@sholland.org>
2022-11-28 07:02:24 +00:00
[RST_BUS_HDMI] = RESET(0xb1c, BIT(16)),
[RST_BUS_HDMI_SUB] = RESET(0xb1c, BIT(17)),
[RST_BUS_TCON_TOP] = RESET(0xb5c, BIT(16)),
[RST_BUS_TCON_LCD0] = RESET(0xb7c, BIT(16)),
[RST_BUS_TCON_TV0] = RESET(0xb9c, BIT(16)),
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
};
clk: sunxi: Use a single driver for all variants Now that all of the variants use the same bind/probe functions and ops, there is no need to have a separate driver for each variant. Since most SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit of firmware size and RAM. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:34 +00:00
const struct ccu_desc h6_ccu_desc = {
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
.gates = h6_gates,
.resets = h6_resets,
clk: sunxi: Store the array sizes in the CCU descriptor The reset array size is currently used for bounds checking in the reset driver. The same bounds check should really be done in the clock driver. Currently, the array size is provided to the reset driver separately from the CCU descriptor, which is a bit strange. Let's do this the usual way, with the array sizes next to the arrays themselves. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> [Andre: add F1C100s support] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-05-09 05:29:31 +00:00
.num_gates = ARRAY_SIZE(h6_gates),
.num_resets = ARRAY_SIZE(h6_resets),
clk: sunxi: Add Allwinner H6 CLK driver Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2018-12-31 10:05:01 +00:00
};
Reference in a new issue Copy permalink