Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Add clock/reset definitions for display-related peripherals, including
the display engine, TCONs, and DSI and HDMI encoders, so those drivers
can be converted to DM clock consumers instead of directly manipulating
the CCU registers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Now that all of the variants use the same bind/probe functions and ops,
there is no need to have a separate driver for each variant. Since most
SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
of firmware size and RAM.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This allows all of the clock drivers to use a common bind function.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The reset array size is currently used for bounds checking in the reset
driver. The same bounds check should really be done in the clock driver.
Currently, the array size is provided to the reset driver separately
from the CCU descriptor, which is a bit strange. Let's do this the usual
way, with the array sizes next to the arrays themselves.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========
Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.
Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
The introduction of the DM pinctrl driver made its probe function enable
all clocks enumerated in the DT. This includes the "CLK_BUS_PIO" (and
variations) gate clock. Also CLK_PLL_PERIPH0 is used by the R_CCU device.
So far we didn't describe those clocks in our clock driver.
As we enable them already in the SPL, the devices happen to work, but
the clock driver still complains about not finding those clocks:
=========
sunxi_set_gate: (CLK#58) unhandled
=========
Add the one-liners that are needed to announce the gate bit for those
clocks, to silence that message on the console.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Currently, the I2C clocks are configured in the sunxi board code. Add
the I2C clocks to the DM clock driver so they can be enabled from the
DM I2C driver using the normal uclass methods.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The XHCI controller has its own clock and reset. Add them.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.
Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.
Signed-off-by: Simon Glass <sjg@chromium.org>
To enable USB support in U-Boot, add the required clock and reset gates
to the H6 clock driver. Once enabled, the generic EHCI/OCHI drivers will
pick them up from there automatically.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> # Pine-H64
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
Allwinner SoCs.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.
We don't advertise the mod clock yet, as this is still handled by the
MMC driver.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Add initial clock driver for Allwinner H6.
- Implement UART bus clocks via ccu_clk_gate table for
H6, so it can accessed in common clk enable and disable
functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for H6,
so it can accessed in common reset deassert and assert
functions from reset-sunxi.c
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
