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clk: sunxi: Use a single driver for all variants

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Now that all of the variants use the same bind/probe functions and ops,
there is no need to have a separate driver for each variant. Since most
SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
of firmware size and RAM.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Samuel Holland 2022-05-09 00:29:34 -05:00 committed by Andre Przywara
parent d39088ad9c
commit 46fa23f9ee
17 changed files with 137 additions and 288 deletions
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20
drivers/clk/sunxi/clk_a10.c
View file

@ -64,27 +64,9 @@ static struct ccu_reset a10_resets[] = {
[RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
};
static const struct ccu_desc a10_ccu_desc = {
const struct ccu_desc a10_ccu_desc = {
.gates = a10_gates,
.resets = a10_resets,
.num_gates = ARRAY_SIZE(a10_gates),
.num_resets = ARRAY_SIZE(a10_resets),
};
static const struct udevice_id a10_ccu_ids[] = {
{ .compatible = "allwinner,sun4i-a10-ccu",
.data = (ulong)&a10_ccu_desc },
{ .compatible = "allwinner,sun7i-a20-ccu",
.data = (ulong)&a10_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun4i_a10) = {
.name = "sun4i_a10_ccu",
.id = UCLASS_CLK,
.of_match = a10_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

20
drivers/clk/sunxi/clk_a10s.c
View file

@ -49,27 +49,9 @@ static struct ccu_reset a10s_resets[] = {
[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
};
static const struct ccu_desc a10s_ccu_desc = {
const struct ccu_desc a10s_ccu_desc = {
.gates = a10s_gates,
.resets = a10s_resets,
.num_gates = ARRAY_SIZE(a10s_gates),
.num_resets = ARRAY_SIZE(a10s_resets),
};
static const struct udevice_id a10s_ccu_ids[] = {
{ .compatible = "allwinner,sun5i-a10s-ccu",
.data = (ulong)&a10s_ccu_desc },
{ .compatible = "allwinner,sun5i-a13-ccu",
.data = (ulong)&a10s_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun5i_a10s) = {
.name = "sun5i_a10s_ccu",
.id = UCLASS_CLK,
.of_match = a10s_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

20
drivers/clk/sunxi/clk_a23.c
View file

@ -68,27 +68,9 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
};
static const struct ccu_desc a23_ccu_desc = {
const struct ccu_desc a23_ccu_desc = {
.gates = a23_gates,
.resets = a23_resets,
.num_gates = ARRAY_SIZE(a23_gates),
.num_resets = ARRAY_SIZE(a23_resets),
};
static const struct udevice_id a23_clk_ids[] = {
{ .compatible = "allwinner,sun8i-a23-ccu",
.data = (ulong)&a23_ccu_desc },
{ .compatible = "allwinner,sun8i-a33-ccu",
.data = (ulong)&a23_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun8i_a23) = {
.name = "sun8i_a23_ccu",
.id = UCLASS_CLK,
.of_match = a23_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_a31.c
View file

@ -89,25 +89,9 @@ static struct ccu_reset a31_resets[] = {
[RST_APB2_UART5] = RESET(0x2d8, BIT(21)),
};
static const struct ccu_desc a31_ccu_desc = {
const struct ccu_desc a31_ccu_desc = {
.gates = a31_gates,
.resets = a31_resets,
.num_gates = ARRAY_SIZE(a31_gates),
.num_resets = ARRAY_SIZE(a31_resets),
};
static const struct udevice_id a31_clk_ids[] = {
{ .compatible = "allwinner,sun6i-a31-ccu",
.data = (ulong)&a31_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun6i_a31) = {
.name = "sun6i_a31_ccu",
.id = UCLASS_CLK,
.of_match = a31_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

22
drivers/clk/sunxi/clk_a31_r.c
View file

@ -28,29 +28,9 @@ static struct ccu_reset a31_r_resets[] = {
[RST_APB0_I2C] = RESET(0x0b0, BIT(6)),
};
static const struct ccu_desc a31_r_ccu_desc = {
const struct ccu_desc a31_r_ccu_desc = {
.gates = a31_r_gates,
.resets = a31_r_resets,
.num_gates = ARRAY_SIZE(a31_r_gates),
.num_resets = ARRAY_SIZE(a31_r_resets),
};
static const struct udevice_id a31_r_clk_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
{ .compatible = "allwinner,sun8i-h3-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
{ .compatible = "allwinner,sun50i-a64-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun6i_a31_r) = {
.name = "sun6i_a31_r_ccu",
.id = UCLASS_CLK,
.of_match = a31_r_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_a64.c
View file

@ -77,25 +77,9 @@ static const struct ccu_reset a64_resets[] = {
[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
};
static const struct ccu_desc a64_ccu_desc = {
const struct ccu_desc a64_ccu_desc = {
.gates = a64_gates,
.resets = a64_resets,
.num_gates = ARRAY_SIZE(a64_gates),
.num_resets = ARRAY_SIZE(a64_resets),
};
static const struct udevice_id a64_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-a64-ccu",
.data = (ulong)&a64_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun50i_a64) = {
.name = "sun50i_a64_ccu",
.id = UCLASS_CLK,
.of_match = a64_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

22
drivers/clk/sunxi/clk_a80.c
View file

@ -74,34 +74,16 @@ static const struct ccu_reset a80_mmc_resets[] = {
[3] = GATE(0xc, BIT(18)),
};
static const struct ccu_desc a80_ccu_desc = {
const struct ccu_desc a80_ccu_desc = {
.gates = a80_gates,
.resets = a80_resets,
.num_gates = ARRAY_SIZE(a80_gates),
.num_resets = ARRAY_SIZE(a80_resets),
};
static const struct ccu_desc a80_mmc_clk_desc = {
const struct ccu_desc a80_mmc_clk_desc = {
.gates = a80_mmc_gates,
.resets = a80_mmc_resets,
.num_gates = ARRAY_SIZE(a80_mmc_gates),
.num_resets = ARRAY_SIZE(a80_mmc_resets),
};
static const struct udevice_id a80_ccu_ids[] = {
{ .compatible = "allwinner,sun9i-a80-ccu",
.data = (ulong)&a80_ccu_desc },
{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
.data = (ulong)&a80_mmc_clk_desc },
{ }
};
U_BOOT_DRIVER(clk_sun9i_a80) = {
.name = "sun9i_a80_ccu",
.id = UCLASS_CLK,
.of_match = a80_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_a83t.c
View file

@ -72,25 +72,9 @@ static struct ccu_reset a83t_resets[] = {
[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
};
static const struct ccu_desc a83t_ccu_desc = {
const struct ccu_desc a83t_ccu_desc = {
.gates = a83t_gates,
.resets = a83t_resets,
.num_gates = ARRAY_SIZE(a83t_gates),
.num_resets = ARRAY_SIZE(a83t_resets),
};
static const struct udevice_id a83t_clk_ids[] = {
{ .compatible = "allwinner,sun8i-a83t-ccu",
.data = (ulong)&a83t_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun8i_a83t) = {
.name = "sun8i_a83t_ccu",
.id = UCLASS_CLK,
.of_match = a83t_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_f1c100s.c
View file

@ -47,25 +47,9 @@ static struct ccu_reset f1c100s_resets[] = {
[RST_BUS_UART2] = RESET(0x2d0, BIT(22)),
};
static const struct ccu_desc f1c100s_ccu_desc = {
const struct ccu_desc f1c100s_ccu_desc = {
.gates = f1c100s_gates,
.resets = f1c100s_resets,
.num_gates = ARRAY_SIZE(f1c100s_gates),
.num_resets = ARRAY_SIZE(f1c100s_resets),
};
static const struct udevice_id f1c100s_clk_ids[] = {
{ .compatible = "allwinner,suniv-f1c100s-ccu",
.data = (ulong)&f1c100s_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_suniv_f1c100s) = {
.name = "suniv_f1c100s_ccu",
.id = UCLASS_CLK,
.of_match = f1c100s_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

20
drivers/clk/sunxi/clk_h3.c
View file

@ -90,27 +90,9 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
};
static const struct ccu_desc h3_ccu_desc = {
const struct ccu_desc h3_ccu_desc = {
.gates = h3_gates,
.resets = h3_resets,
.num_gates = ARRAY_SIZE(h3_gates),
.num_resets = ARRAY_SIZE(h3_resets),
};
static const struct udevice_id h3_ccu_ids[] = {
{ .compatible = "allwinner,sun8i-h3-ccu",
.data = (ulong)&h3_ccu_desc },
{ .compatible = "allwinner,sun50i-h5-ccu",
.data = (ulong)&h3_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun8i_h3) = {
.name = "sun8i_h3_ccu",
.id = UCLASS_CLK,
.of_match = h3_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_h6.c
View file

@ -91,25 +91,9 @@ static struct ccu_reset h6_resets[] = {
[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
};
static const struct ccu_desc h6_ccu_desc = {
const struct ccu_desc h6_ccu_desc = {
.gates = h6_gates,
.resets = h6_resets,
.num_gates = ARRAY_SIZE(h6_gates),
.num_resets = ARRAY_SIZE(h6_resets),
};
static const struct udevice_id h6_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h6-ccu",
.data = (ulong)&h6_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun50i_h6) = {
.name = "sun50i_h6_ccu",
.id = UCLASS_CLK,
.of_match = h6_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_h616.c
View file

@ -109,25 +109,9 @@ static struct ccu_reset h616_resets[] = {
[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
};
static const struct ccu_desc h616_ccu_desc = {
const struct ccu_desc h616_ccu_desc = {
.gates = h616_gates,
.resets = h616_resets,
.num_gates = ARRAY_SIZE(h616_gates),
.num_resets = ARRAY_SIZE(h616_resets),
};
static const struct udevice_id h616_ccu_ids[] = {
{ .compatible = "allwinner,sun50i-h616-ccu",
.data = (ulong)&h616_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun50i_h616) = {
.name = "sun50i_h616_ccu",
.id = UCLASS_CLK,
.of_match = h616_ccu_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

20
drivers/clk/sunxi/clk_h6_r.c
View file

@ -34,27 +34,9 @@ static struct ccu_reset h6_r_resets[] = {
[RST_R_APB1_W1] = RESET(0x1ec, BIT(16)),
};
static const struct ccu_desc h6_r_ccu_desc = {
const struct ccu_desc h6_r_ccu_desc = {
.gates = h6_r_gates,
.resets = h6_r_resets,
.num_gates = ARRAY_SIZE(h6_r_gates),
.num_resets = ARRAY_SIZE(h6_r_resets),
};
static const struct udevice_id h6_r_clk_ids[] = {
{ .compatible = "allwinner,sun50i-h6-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
{ .compatible = "allwinner,sun50i-h616-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun50i_h6_r) = {
.name = "sun50i_h6_r_ccu",
.id = UCLASS_CLK,
.of_match = h6_r_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

18
drivers/clk/sunxi/clk_r40.c
View file

@ -99,25 +99,9 @@ static struct ccu_reset r40_resets[] = {
[RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
};
static const struct ccu_desc r40_ccu_desc = {
const struct ccu_desc r40_ccu_desc = {
.gates = r40_gates,
.resets = r40_resets,
.num_gates = ARRAY_SIZE(r40_gates),
.num_resets = ARRAY_SIZE(r40_resets),
};
static const struct udevice_id r40_clk_ids[] = {
{ .compatible = "allwinner,sun8i-r40-ccu",
.data = (ulong)&r40_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun8i_r40) = {
.name = "sun8i_r40_ccu",
.id = UCLASS_CLK,
.of_match = r40_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

123
drivers/clk/sunxi/clk_sunxi.c
View file

@ -67,12 +67,12 @@ struct clk_ops sunxi_clk_ops = {
.disable = sunxi_clk_disable,
};
int sunxi_clk_bind(struct udevice *dev)
static int sunxi_clk_bind(struct udevice *dev)
{
return sunxi_reset_bind(dev);
}
int sunxi_clk_probe(struct udevice *dev)
static int sunxi_clk_probe(struct udevice *dev)
{
struct ccu_priv *priv = dev_get_priv(dev);
struct clk_bulk clk_bulk;
@ -97,3 +97,122 @@ int sunxi_clk_probe(struct udevice *dev)
return 0;
}
extern const struct ccu_desc a10_ccu_desc;
extern const struct ccu_desc a10s_ccu_desc;
extern const struct ccu_desc a23_ccu_desc;
extern const struct ccu_desc a31_ccu_desc;
extern const struct ccu_desc a31_r_ccu_desc;
extern const struct ccu_desc a64_ccu_desc;
extern const struct ccu_desc a80_ccu_desc;
extern const struct ccu_desc a80_mmc_clk_desc;
extern const struct ccu_desc a83t_ccu_desc;
extern const struct ccu_desc f1c100s_ccu_desc;
extern const struct ccu_desc h3_ccu_desc;
extern const struct ccu_desc h6_ccu_desc;
extern const struct ccu_desc h616_ccu_desc;
extern const struct ccu_desc h6_r_ccu_desc;
extern const struct ccu_desc r40_ccu_desc;
extern const struct ccu_desc v3s_ccu_desc;
static const struct udevice_id sunxi_clk_ids[] = {
#ifdef CONFIG_CLK_SUN4I_A10
{ .compatible = "allwinner,sun4i-a10-ccu",
.data = (ulong)&a10_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN5I_A10S
{ .compatible = "allwinner,sun5i-a10s-ccu",
.data = (ulong)&a10s_ccu_desc },
{ .compatible = "allwinner,sun5i-a13-ccu",
.data = (ulong)&a10s_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31
{ .compatible = "allwinner,sun6i-a31-ccu",
.data = (ulong)&a31_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN4I_A10
{ .compatible = "allwinner,sun7i-a20-ccu",
.data = (ulong)&a10_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_A23
{ .compatible = "allwinner,sun8i-a23-ccu",
.data = (ulong)&a23_ccu_desc },
{ .compatible = "allwinner,sun8i-a33-ccu",
.data = (ulong)&a23_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_A83T
{ .compatible = "allwinner,sun8i-a83t-ccu",
.data = (ulong)&a83t_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31_R
{ .compatible = "allwinner,sun8i-a83t-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_H3
{ .compatible = "allwinner,sun8i-h3-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31_R
{ .compatible = "allwinner,sun8i-h3-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_R40
{ .compatible = "allwinner,sun8i-r40-ccu",
.data = (ulong)&r40_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_V3S
{ .compatible = "allwinner,sun8i-v3-ccu",
.data = (ulong)&v3s_ccu_desc },
{ .compatible = "allwinner,sun8i-v3s-ccu",
.data = (ulong)&v3s_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN9I_A80
{ .compatible = "allwinner,sun9i-a80-ccu",
.data = (ulong)&a80_ccu_desc },
{ .compatible = "allwinner,sun9i-a80-mmc-config-clk",
.data = (ulong)&a80_mmc_clk_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_A64
{ .compatible = "allwinner,sun50i-a64-ccu",
.data = (ulong)&a64_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN6I_A31_R
{ .compatible = "allwinner,sun50i-a64-r-ccu",
.data = (ulong)&a31_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN8I_H3
{ .compatible = "allwinner,sun50i-h5-ccu",
.data = (ulong)&h3_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6
{ .compatible = "allwinner,sun50i-h6-ccu",
.data = (ulong)&h6_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6_R
{ .compatible = "allwinner,sun50i-h6-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H616
{ .compatible = "allwinner,sun50i-h616-ccu",
.data = (ulong)&h616_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUN50I_H6_R
{ .compatible = "allwinner,sun50i-h616-r-ccu",
.data = (ulong)&h6_r_ccu_desc },
#endif
#ifdef CONFIG_CLK_SUNIV_F1C100S
{ .compatible = "allwinner,suniv-f1c100s-ccu",
.data = (ulong)&f1c100s_ccu_desc },
#endif
{ }
};
U_BOOT_DRIVER(sunxi_clk) = {
.name = "sunxi_clk",
.id = UCLASS_CLK,
.of_match = sunxi_clk_ids,
.bind = sunxi_clk_bind,
.probe = sunxi_clk_probe,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
};

20
drivers/clk/sunxi/clk_v3s.c
View file

@ -49,27 +49,9 @@ static struct ccu_reset v3s_resets[] = {
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
};
static const struct ccu_desc v3s_ccu_desc = {
const struct ccu_desc v3s_ccu_desc = {
.gates = v3s_gates,
.resets = v3s_resets,
.num_gates = ARRAY_SIZE(v3s_gates),
.num_resets = ARRAY_SIZE(v3s_resets),
};
static const struct udevice_id v3s_clk_ids[] = {
{ .compatible = "allwinner,sun8i-v3s-ccu",
.data = (ulong)&v3s_ccu_desc },
{ .compatible = "allwinner,sun8i-v3-ccu",
.data = (ulong)&v3s_ccu_desc },
{ }
};
U_BOOT_DRIVER(clk_sun8i_v3s) = {
.name = "sun8i_v3s_ccu",
.id = UCLASS_CLK,
.of_match = v3s_clk_ids,
.priv_auto = sizeof(struct ccu_priv),
.ops = &sunxi_clk_ops,
.probe = sunxi_clk_probe,
.bind = sunxi_clk_bind,
};

12
include/clk/sunxi.h
View file

@ -85,18 +85,6 @@ struct ccu_priv {
const struct ccu_desc *desc;
};
/**
* sunxi_clk_bind - common sunxi clock bind
* @dev: clock device
*/
int sunxi_clk_bind(struct udevice *dev);
/**
* sunxi_clk_probe - common sunxi clock probe
* @dev: clock device
*/
int sunxi_clk_probe(struct udevice *dev);
extern struct clk_ops sunxi_clk_ops;
/**