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u-boot/drivers/timer/Kconfig

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dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
menu "Timer Support"
config TIMER
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
bool "Enable driver model for timer drivers"
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
depends on DM
help
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
Enable driver model for timer access. It uses the same API as
lib/time.c, but now implemented by the uclass. The first timer
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
will be used. The timer is usually a 32 bits free-running up
counter. There may be no real tick, and no timer interrupt.
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28 15:38:42 +00:00
config SPL_TIMER
bool "Enable driver model for timer drivers in SPL"
depends on TIMER && SPL
help
Enable support for timer drivers in SPL. These can be used to get
a timer value when in SPL, or perhaps for implementing a delay
function. This enables the drivers in drivers/timer as part of an
SPL build.
config TPL_TIMER
bool "Enable driver model for timer drivers in TPL"
depends on TIMER && TPL
help
Enable support for timer drivers in TPL. These can be used to get
a timer value when in TPL, or perhaps for implementing a delay
function. This enables the drivers in drivers/timer as part of an
TPL build.
vpl: Add Kconfig options for VPL Add VPL versions of commonly used Kconfig options. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-04-30 06:56:53 +00:00
config VPL_TIMER
bool "Enable driver model for timer drivers in VPL"
depends on TIMER && VPL
default y if TPL_TIMER
help
Enable support for timer drivers in VPL. These can be used to get
a timer value when in VPL, or perhaps for implementing a delay
function. This enables the drivers in drivers/timer as part of an
TPL build.
timer: Provide an early timer In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-24 16:14:49 +00:00
config TIMER_EARLY
bool "Allow timer to be used early in U-Boot"
depends on TIMER
Enable CONFIG_TIMER_EARLY with bootstage In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-09-02 23:02:24 +00:00
# initr_bootstage() requires a timer and is called before initr_dm()
# so only the early timer is available
default y if X86 && BOOTSTAGE
timer: Provide an early timer In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-24 16:14:49 +00:00
help
In some cases the timer must be accessible before driver model is
active. Examples include when using CONFIG_TRACE to trace U-Boot's
execution before driver model is set up. Enable this option to
use an early timer. These functions must be supported by your timer
driver: timer_early_get_count() and timer_early_get_rate().
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
2015-10-22 14:28:53 +00:00
config ALTERA_TIMER
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
bool "Altera timer support"
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
2015-10-22 14:28:53 +00:00
depends on TIMER
help
dm: timer: Fix several nits This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:14 +00:00
Select this to enable a timer for Altera devices. Please find
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
2015-10-22 14:28:53 +00:00
details on the "Embedded Peripherals IP User Guide" of Altera.
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 01:46:57 +00:00
config ANDES_PLMT_TIMER
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
2020-10-26 01:46:56 +00:00
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
config ARC_TIMER
bool "ARC timer support"
depends on TIMER && ARC && CLK
help
Select this to enable built-in ARC timers.
ARC cores may have up to 2 built-in timers: timer0 and timer1,
usually at least one of them exists. Either of them is supported
in U-Boot.
config AST_TIMER
bool "Aspeed ast2400/ast2500 timer support"
depends on TIMER
default y if ARCH_ASPEED
help
Select this to enable timer for Aspeed ast2400/ast2500 devices.
This is a simple sys timer driver, it is compatible with lib/time.c,
but does not support any interrupts. Even though SoC has 8 hardware
counters, they are all treated as a single device by this driver.
This is mostly because they all share several registers which
makes it difficult to completely separate them.
config ATCPIT100_TIMER
bool "ATCPIT100 timer support"
depends on TIMER
help
Select this to enable a ATCPIT100 timer which will be embedded
in AE3XX, AE250 boards.
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-08-15 09:40:26 +00:00
config ATMEL_PIT_TIMER
bool "Atmel periodic interval timer support"
depends on TIMER
help
Select this to enable a periodic interval timer for Atmel devices,
it is designed to offer maximum accuracy and efficient management,
even for systems with long response time.
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-04-04 08:35:51 +00:00
config SPL_ATMEL_PIT_TIMER
bool "Atmel periodic interval timer support in SPL"
depends on SPL_TIMER
help
Select this to enable a periodic interval timer for Atmel devices,
it is designed to offer maximum accuracy and efficient management,
even for systems with long response time.
Select this to be available in SPL.
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2022-03-31 08:55:06 +00:00
config ATMEL_TCB_TIMER
bool "Atmel timer counter support"
depends on TIMER
depends on ARCH_AT91
help
Select this to enable the use of the timer counter as a monotonic
counter.
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-04-04 08:35:50 +00:00
config SPL_ATMEL_TCB_TIMER
bool "Atmel timer counter support in SPL"
depends on SPL_TIMER
depends on ARCH_AT91
help
Select this to enable the use of the timer counter as a monotonic
counter in SPL.
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-17 11:40:46 +00:00
config CADENCE_TTC_TIMER
bool "Cadence TTC (Triple Timer Counter)"
depends on TIMER
help
Enables support for the cadence ttc driver. This driver is present
on Xilinx Zynq and ZynqMP SoCs.
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-18 13:58:32 +00:00
config DESIGNWARE_APB_TIMER
bool "Designware APB Timer"
depends on TIMER
help
Enables support for the Designware APB Timer driver. This timer is
present on Altera SoCFPGA SoCs.
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
2022-06-08 21:21:35 +00:00
config GXP_TIMER
bool "HPE GXP Timer"
depends on TIMER
help
Enables support for the GXP Timer driver. This timer is
present on HPE GXP SoCs.
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
config MPC83XX_TIMER
bool "MPC83xx timer support"
depends on TIMER
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:24 +00:00
help
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-11-13 08:11:24 +00:00
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-04 15:30:58 +00:00
config RENESAS_OSTM_TIMER
bool "Renesas RZ/A1 R7S72100 OSTM Timer"
depends on TIMER
help
Enables support for the Renesas OSTM Timer driver.
This timer is present on Renesas RZ/A1 R7S72100 SoCs.
x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-28 04:00:22 +00:00
config X86_TSC_TIMER_FREQ
int "x86 TSC timer frequency in Hz"
x86: tsc: Introduce config option for early timer frequency So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-14 03:52:10 +00:00
depends on X86_TSC_TIMER
x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-28 04:00:22 +00:00
default 1000000000
x86: tsc: Introduce config option for early timer frequency So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-14 03:52:10 +00:00
help
x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ Currently there are two places to specify the x86 TSC timer frequency with one in Kconfig used for early timer and the other one in device tree used when the frequency cannot be determined from hardware. This may potentially create an inconsistent config where the 2 values do not match. Let's use the one specified in Kconfig in the device tree as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-28 04:00:22 +00:00
Sets the estimated CPU frequency in Hz when TSC is used as the
x86: tsc: Introduce config option for early timer frequency So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-14 03:52:10 +00:00
early timer and the frequency can neither be calibrated via some
hardware ways, nor got from device tree at the time when device
tree is not available yet.
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-01-04 17:45:15 +00:00
config NOMADIK_MTU_TIMER
bool "Nomadik MTU Timer"
depends on TIMER
help
Enables support for the Nomadik Multi Timer Unit (MTU),
used in ST-Ericsson Ux500 SoCs.
The MTU provides 4 decrementing free-running timers.
At the moment, only the first timer is used by the driver.
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com>
2022-04-19 05:32:22 +00:00
config NPCM_TIMER
bool "Nuvoton NPCM timer support"
depends on TIMER
help
Select this to enable a timer on Nuvoton NPCM SoCs.
NPCM timer module has 5 down-counting timers, only the first timer
is used to implement timer ops. No support for early timer and
boot timer.
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2015-12-24 10:38:07 +00:00
config OMAP_TIMER
bool "Omap timer support"
depends on TIMER
help
Select this to enable an timer for Omap devices.
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:27 +00:00
config RISCV_TIMER
bool "RISC-V timer support"
depends on TIMER && RISCV
help
riscv: Rework riscv timer driver to only support S-mode The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
2020-09-28 14:52:21 +00:00
Select this to enable support for a generic RISC-V S-Mode timer
driver.
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
2018-12-12 14:12:27 +00:00
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
config ROCKCHIP_TIMER
bool "Rockchip timer support"
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
depends on TIMER
help
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
Select this to enable support for the timer found on
Rockchip devices.
config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
help
Select this to enable an emulated timer for sandbox. It gets
time from host os.
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-18 21:44:55 +00:00
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-02-21 12:37:05 +00:00
config STI_TIMER
bool "STi timer support"
depends on TIMER
default y if ARCH_STI
help
Select this to enable a timer for STi devices.
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-02-07 09:44:45 +00:00
config STM32_TIMER
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
bool "STM32 timer support"
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-02-07 09:44:45 +00:00
depends on TIMER
help
Select this to enable support for the timer found on
STM32 devices.
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
config X86_TSC_TIMER
bool "x86 Time-Stamp Counter (TSC) timer support"
depends on TIMER && X86
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:38 +00:00
help
timer: Sort Kconfig driver entries This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-10-11 05:07:02 +00:00
Select this to enable Time-Stamp Counter (TSC) timer for x86.
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-08-06 08:23:38 +00:00
x86: timer: use a timer base of 0 On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:41:49 +00:00
config X86_TSC_READ_BASE
bool "Read the TSC timer base on start-up"
depends on X86_TSC_TIMER
help
On x86 platforms the TSC timer tick starts at the value 0 on reset.
This it makes no sense to read the timer on boot and use that as the
base, since we will miss some time taken to load U-Boot, etc. This
delay is controlled by the SoC and we cannot reduce it, but for
bootstage we want to record the time since reset as accurately as
possible.
The only exception is when U-Boot is used as a secondary bootloader,
where this option should be enabled.
x86: timer: Reduce timer code size in TPL on Intel CPUs Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:41:50 +00:00
config TPL_X86_TSC_TIMER_NATIVE
bool "x86 TSC timer uses native calibration"
depends on TPL && X86_TSC_TIMER
help
Selects native timer calibration for TPL and don't include the other
methods in the code. This helps to reduce code size in TPL and works
on fairly modern Intel chips. Code-size reductions is about 700
bytes.
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-11-15 02:07:56 +00:00
config MTK_TIMER
bool "MediaTek timer support"
depends on TIMER
help
Select this to enable support for the timer found on
MediaTek devices.
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2020-09-07 15:36:33 +00:00
config MCHP_PIT64B_TIMER
bool "Microchip 64-bit periodic interval timer support"
depends on TIMER
help
Select this to enable support for Microchip 64-bit periodic
interval timer.
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer]
2021-05-13 10:18:31 +00:00
config IMX_GPT_TIMER
bool "NXP i.MX GPT timer support"
depends on TIMER
help
Select this to enable support for the timer found on
NXP i.MX devices.
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24 12:16:32 +00:00
config XILINX_TIMER
bool "Xilinx timer support"
depends on TIMER
select REGMAP
timer: Add SPL_REGMAP dependency for Xilinx timer Add SPL_REGMAP dependency when SPL is enabled. This can avoid compilation issues if timer is selected but SPL_REGMAP not. Reported-by: Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/8f6c187e04cb3127bf5148ae2dbbdf55b25ea544.1655982509.git.michal.simek@amd.com
2022-06-23 11:08:30 +00:00
select SPL_REGMAP if SPL
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24 12:16:32 +00:00
help
Select this to enable support for the timer found on
any Xilinx boards (axi timer).
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-09 05:46:34 +00:00
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