2017-02-07 03:17:34 +00:00
|
|
|
|
|
|
|
|
config BITBANGMII
|
|
|
|
|
bool "Bit-banged ethernet MII management channel support"
|
|
|
|
|
|
|
|
|
|
config MV88E6352_SWITCH
|
|
|
|
|
bool "Marvell 88E6352 switch support"
|
|
|
|
|
|
|
|
|
|
menuconfig PHYLIB
|
|
|
|
|
bool "Ethernet PHY (physical media interface) support"
|
2018-02-06 12:23:52 +00:00
|
|
|
depends on NET
|
2017-02-07 03:17:34 +00:00
|
|
|
help
|
|
|
|
|
Enable Ethernet PHY (physical media interface) support.
|
|
|
|
|
|
|
|
|
|
if PHYLIB
|
|
|
|
|
|
2018-03-30 16:52:16 +00:00
|
|
|
config PHY_ADDR_ENABLE
|
|
|
|
|
bool "Limit phy address"
|
|
|
|
|
default y if ARCH_SUNXI
|
|
|
|
|
help
|
|
|
|
|
Select this if you want to control which phy address is used
|
|
|
|
|
|
|
|
|
|
if PHY_ADDR_ENABLE
|
2018-02-02 13:53:38 +00:00
|
|
|
config PHY_ADDR
|
|
|
|
|
int "PHY address"
|
|
|
|
|
default 1 if ARCH_SUNXI
|
|
|
|
|
default 0
|
|
|
|
|
help
|
|
|
|
|
The address of PHY on MII bus. Usually in range of 0 to 31.
|
2018-03-30 16:52:16 +00:00
|
|
|
endif
|
2018-02-02 13:53:38 +00:00
|
|
|
|
2017-12-09 22:59:54 +00:00
|
|
|
config B53_SWITCH
|
|
|
|
|
bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
|
|
|
|
|
help
|
|
|
|
|
Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
|
|
|
|
|
This currently supports BCM53125 and similar models.
|
|
|
|
|
|
|
|
|
|
if B53_SWITCH
|
|
|
|
|
|
|
|
|
|
config B53_CPU_PORT
|
|
|
|
|
int "CPU port"
|
|
|
|
|
default 8
|
|
|
|
|
|
|
|
|
|
config B53_PHY_PORTS
|
|
|
|
|
hex "Bitmask of PHY ports"
|
|
|
|
|
|
|
|
|
|
endif # B53_SWITCH
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config MV88E61XX_SWITCH
|
2019-10-26 23:14:41 +00:00
|
|
|
bool "Marvell MV88E61xx Ethernet switch PHY support."
|
2017-02-07 03:17:34 +00:00
|
|
|
|
2017-03-17 14:29:51 +00:00
|
|
|
if MV88E61XX_SWITCH
|
|
|
|
|
|
|
|
|
|
config MV88E61XX_CPU_PORT
|
|
|
|
|
int "CPU Port"
|
|
|
|
|
|
|
|
|
|
config MV88E61XX_PHY_PORTS
|
|
|
|
|
hex "Bitmask of PHY Ports"
|
|
|
|
|
|
|
|
|
|
config MV88E61XX_FIXED_PORTS
|
|
|
|
|
hex "Bitmask of PHYless serdes Ports"
|
|
|
|
|
|
|
|
|
|
endif # MV88E61XX_SWITCH
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config PHYLIB_10G
|
|
|
|
|
bool "Generic 10G PHY support"
|
|
|
|
|
|
2018-09-18 21:49:36 +00:00
|
|
|
menuconfig PHY_AQUANTIA
|
2017-02-07 03:17:34 +00:00
|
|
|
bool "Aquantia Ethernet PHYs support"
|
2018-09-18 21:49:35 +00:00
|
|
|
select PHY_GIGE
|
|
|
|
|
select PHYLIB_10G
|
2017-02-07 03:17:34 +00:00
|
|
|
|
2018-09-18 21:49:36 +00:00
|
|
|
config PHY_AQUANTIA_UPLOAD_FW
|
|
|
|
|
bool "Aquantia firmware loading support"
|
|
|
|
|
depends on PHY_AQUANTIA
|
|
|
|
|
help
|
|
|
|
|
Aquantia PHYs use firmware which can be either loaded automatically
|
|
|
|
|
from storage directly attached to the phy or loaded by the boot loader
|
|
|
|
|
via MDIO commands. The firmware is loaded from a file, specified by
|
|
|
|
|
the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
|
|
|
|
|
|
|
|
|
|
config PHY_AQUANTIA_FW_PART
|
|
|
|
|
string "Aquantia firmware partition"
|
|
|
|
|
depends on PHY_AQUANTIA_UPLOAD_FW
|
|
|
|
|
help
|
|
|
|
|
Partition containing the firmware file.
|
|
|
|
|
|
|
|
|
|
config PHY_AQUANTIA_FW_NAME
|
|
|
|
|
string "Aquantia firmware filename"
|
|
|
|
|
depends on PHY_AQUANTIA_UPLOAD_FW
|
|
|
|
|
help
|
|
|
|
|
Firmware filename.
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config PHY_ATHEROS
|
|
|
|
|
bool "Atheros Ethernet PHYs support"
|
|
|
|
|
|
|
|
|
|
config PHY_BROADCOM
|
|
|
|
|
bool "Broadcom Ethernet PHYs support"
|
|
|
|
|
|
|
|
|
|
config PHY_CORTINA
|
|
|
|
|
bool "Cortina Ethernet PHYs support"
|
|
|
|
|
|
2020-10-29 13:46:15 +00:00
|
|
|
config SYS_CORTINA_NO_FW_UPLOAD
|
|
|
|
|
bool "Cortina firmware loading support"
|
|
|
|
|
depends on PHY_CORTINA
|
|
|
|
|
help
|
|
|
|
|
Cortina phy has provision to store phy firmware in attached dedicated
|
|
|
|
|
EEPROM. And boards designed with such EEPROM does not require firmware
|
|
|
|
|
upload.
|
|
|
|
|
|
2019-11-26 22:32:43 +00:00
|
|
|
choice
|
|
|
|
|
prompt "Location of the Cortina firmware"
|
|
|
|
|
default SYS_CORTINA_FW_IN_NOR
|
|
|
|
|
depends on PHY_CORTINA
|
|
|
|
|
|
|
|
|
|
config SYS_CORTINA_FW_IN_MMC
|
|
|
|
|
bool "Cortina firmware in MMC"
|
|
|
|
|
|
|
|
|
|
config SYS_CORTINA_FW_IN_NAND
|
|
|
|
|
bool "Cortina firmware in NAND flash"
|
|
|
|
|
|
|
|
|
|
config SYS_CORTINA_FW_IN_NOR
|
|
|
|
|
bool "Cortina firmware in NOR flash"
|
|
|
|
|
|
|
|
|
|
config SYS_CORTINA_FW_IN_REMOTE
|
|
|
|
|
bool "Cortina firmware in remote device"
|
|
|
|
|
|
|
|
|
|
config SYS_CORTINA_FW_IN_SPIFLASH
|
|
|
|
|
bool "Cortina firmware in SPI flash"
|
|
|
|
|
|
|
|
|
|
endchoice
|
|
|
|
|
|
2021-08-10 05:50:07 +00:00
|
|
|
config CORTINA_FW_ADDR
|
|
|
|
|
hex "Cortina Firmware Address"
|
|
|
|
|
depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
|
|
|
|
|
default 0x0
|
|
|
|
|
|
|
|
|
|
config CORTINA_FW_LENGTH
|
|
|
|
|
hex "Cortina Firmware Length"
|
|
|
|
|
depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
|
|
|
|
|
default 0x40000
|
|
|
|
|
|
2021-01-14 21:34:12 +00:00
|
|
|
config PHY_CORTINA_ACCESS
|
|
|
|
|
bool "Cortina Access Ethernet PHYs support"
|
|
|
|
|
default y
|
|
|
|
|
depends on CORTINA_NI_ENET
|
|
|
|
|
help
|
|
|
|
|
Cortina Access Ethernet PHYs init process
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config PHY_DAVICOM
|
|
|
|
|
bool "Davicom Ethernet PHYs support"
|
|
|
|
|
|
|
|
|
|
config PHY_ET1011C
|
|
|
|
|
bool "LSI TruePHY ET1011C support"
|
|
|
|
|
|
|
|
|
|
config PHY_LXT
|
|
|
|
|
bool "LXT971 Ethernet PHY support"
|
|
|
|
|
|
|
|
|
|
config PHY_MARVELL
|
|
|
|
|
bool "Marvell Ethernet PHYs support"
|
|
|
|
|
|
2017-10-18 08:02:10 +00:00
|
|
|
config PHY_MESON_GXL
|
|
|
|
|
bool "Amlogic Meson GXL Internal PHY support"
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config PHY_MICREL
|
|
|
|
|
bool "Micrel Ethernet PHYs support"
|
2017-03-26 16:50:23 +00:00
|
|
|
help
|
|
|
|
|
Enable support for the GbE PHYs manufactured by Micrel (now
|
2019-03-06 12:48:27 +00:00
|
|
|
a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
|
|
|
|
|
KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
|
|
|
|
|
family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
|
|
|
|
|
KSZ90x1 family support" is selected).
|
2017-03-26 16:50:23 +00:00
|
|
|
|
|
|
|
|
if PHY_MICREL
|
|
|
|
|
|
|
|
|
|
config PHY_MICREL_KSZ9021
|
2017-07-07 18:37:00 +00:00
|
|
|
bool
|
net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-07 18:36:57 +00:00
|
|
|
select PHY_MICREL_KSZ90X1
|
|
|
|
|
|
2017-03-26 16:50:23 +00:00
|
|
|
config PHY_MICREL_KSZ9031
|
2017-07-07 18:37:00 +00:00
|
|
|
bool
|
net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-07 18:36:57 +00:00
|
|
|
select PHY_MICREL_KSZ90X1
|
|
|
|
|
|
|
|
|
|
config PHY_MICREL_KSZ90X1
|
|
|
|
|
bool "Micrel KSZ90x1 family support"
|
|
|
|
|
select PHY_GIGE
|
|
|
|
|
help
|
|
|
|
|
Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
|
|
|
|
|
enabled, the extended register read/write for KSZ90x1 PHYs
|
|
|
|
|
is supported through the 'mdio' command and any RGMII signal
|
|
|
|
|
delays configured in the device tree will be applied to the
|
|
|
|
|
PHY during initialization.
|
|
|
|
|
|
|
|
|
|
config PHY_MICREL_KSZ8XXX
|
|
|
|
|
bool "Micrel KSZ8xxx family support"
|
|
|
|
|
help
|
2019-03-06 12:48:27 +00:00
|
|
|
Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
|
net: phy: micrel: Separate KSZ9000 drivers from KSZ8000 drivers
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-07-07 18:36:57 +00:00
|
|
|
(now a part of Microchip). This includes drivers for the KSZ804,
|
|
|
|
|
KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
|
|
|
|
|
|
2017-03-26 16:50:23 +00:00
|
|
|
endif # PHY_MICREL
|
2017-02-07 03:17:34 +00:00
|
|
|
|
2016-12-09 22:15:17 +00:00
|
|
|
config PHY_MSCC
|
|
|
|
|
bool "Microsemi Corp Ethernet PHYs support"
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config PHY_NATSEMI
|
|
|
|
|
bool "National Semiconductor Ethernet PHYs support"
|
|
|
|
|
|
2021-06-18 18:58:30 +00:00
|
|
|
config PHY_NXP_C45_TJA11XX
|
|
|
|
|
tristate "NXP C45 TJA11XX PHYs"
|
|
|
|
|
help
|
|
|
|
|
Enable support for NXP C45 TJA11XX PHYs.
|
|
|
|
|
Currently supports only the TJA1103 PHY.
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config PHY_REALTEK
|
|
|
|
|
bool "Realtek Ethernet PHYs support"
|
|
|
|
|
|
2018-02-14 23:02:15 +00:00
|
|
|
config RTL8211E_PINE64_GIGABIT_FIX
|
|
|
|
|
bool "Fix gigabit throughput on some Pine64+ models"
|
|
|
|
|
depends on PHY_REALTEK
|
|
|
|
|
help
|
|
|
|
|
Configure the Realtek RTL8211E found on some Pine64+ models differently to
|
|
|
|
|
fix throughput on Gigabit links, turning off all internal delays in the
|
|
|
|
|
process. The settings that this touches are not documented in the CONFREG
|
|
|
|
|
section of the RTL8211E datasheet, but come from Realtek by way of the
|
|
|
|
|
Pine64 engineering team.
|
|
|
|
|
|
2017-02-07 03:17:34 +00:00
|
|
|
config RTL8211X_PHY_FORCE_MASTER
|
|
|
|
|
bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
|
|
|
|
|
depends on PHY_REALTEK
|
|
|
|
|
help
|
|
|
|
|
Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
|
|
|
|
|
This can work around link stability and data corruption issues on gigabit
|
|
|
|
|
links which can occur in slave mode on certain PHYs, e.g. on the
|
|
|
|
|
RTL8211C(L).
|
|
|
|
|
|
|
|
|
|
Please note that two directly connected devices (i.e. via crossover cable)
|
|
|
|
|
will not be able to establish a link between each other if they both force
|
|
|
|
|
master mode. Multiple devices forcing master mode when connected by a
|
|
|
|
|
network switch do not pose a problem as the switch configures its affected
|
|
|
|
|
ports into slave mode.
|
|
|
|
|
|
|
|
|
|
This option only affects gigabit links. If you must establish a direct
|
|
|
|
|
connection between two devices which both force master mode, try forcing
|
|
|
|
|
the link speed to 100MBit/s.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2019-01-24 08:54:37 +00:00
|
|
|
config RTL8211F_PHY_FORCE_EEE_RXC_ON
|
|
|
|
|
bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
|
|
|
|
|
depends on PHY_REALTEK
|
|
|
|
|
help
|
|
|
|
|
The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
|
|
|
|
|
transitions to/from a lower power consumption level (Low Power Idle
|
|
|
|
|
mode) based on link utilization. When no packets are being
|
|
|
|
|
transmitted, the system goes to Low Power Idle mode to save power.
|
|
|
|
|
|
|
|
|
|
Under particular circumstances this setting can cause issues where
|
|
|
|
|
the PHY is unable to transmit or receive any packet when in LPI mode.
|
|
|
|
|
The problem is caused when the PHY is configured to stop receiving
|
|
|
|
|
the xMII clock while it is signaling LPI. For some PHYs the bit
|
|
|
|
|
configuring this behavior is set by the Linux kernel, causing the
|
|
|
|
|
issue in U-Boot on reboot if the PHY retains the register value.
|
|
|
|
|
|
|
|
|
|
Default n, which means that the PHY state is not changed. To work
|
|
|
|
|
around the issues, change this setting to y.
|
|
|
|
|
|
2020-05-09 14:25:11 +00:00
|
|
|
config RTL8201F_PHY_S700_RMII_TIMINGS
|
|
|
|
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bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
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depends on PHY_REALTEK
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help
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This provides an option to configure specific timing requirements (needed
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for proper PHY operations) for the PHY module present on ACTION SEMI S700
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based cubieboard7. Exact timing requiremnets seems to be SoC specific
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(and it's undocumented) that comes from vendor code itself.
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2017-02-07 03:17:34 +00:00
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config PHY_SMSC
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bool "Microchip(SMSC) Ethernet PHYs support"
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config PHY_TERANETICS
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bool "Teranetics Ethernet PHYs support"
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config PHY_TI
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bool "Texas Instruments Ethernet PHYs support"
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2020-05-04 21:14:39 +00:00
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---help---
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Adds PHY registration support for TI PHYs.
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config PHY_TI_DP83867
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select PHY_TI
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bool "Texas Instruments Ethernet DP83867 PHY support"
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---help---
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Adds support for the TI DP83867 1Gbit PHY.
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2017-02-07 03:17:34 +00:00
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2020-05-04 21:14:40 +00:00
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config PHY_TI_GENERIC
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select PHY_TI
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bool "Texas Instruments Generic Ethernet PHYs support"
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|
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---help---
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Adds support for Generic TI PHYs that don't need special handling but
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the PHY name is associated with a PHY ID.
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2017-02-07 03:17:34 +00:00
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config PHY_VITESSE
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bool "Vitesse Ethernet PHYs support"
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config PHY_XILINX
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bool "Xilinx Ethernet PHYs support"
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2018-11-27 06:19:11 +00:00
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config PHY_XILINX_GMII2RGMII
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bool "Xilinx GMII to RGMII Ethernet PHYs support"
|
2021-03-14 12:14:51 +00:00
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|
depends on DM_ETH
|
2018-11-27 06:19:11 +00:00
|
|
|
help
|
|
|
|
|
This adds support for Xilinx GMII to RGMII IP core. This IP acts
|
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|
|
as bridge between MAC connected over GMII and external phy that
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|
is connected over RGMII interface.
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|
2017-03-23 14:11:43 +00:00
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|
config PHY_FIXED
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bool "Fixed-Link PHY"
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depends on DM_ETH
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help
|
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|
|
Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
|
|
|
|
|
connection (MII, RGMII, ...).
|
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|
|
There is nothing like autoneogation and so
|
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|
|
|
on, the link is always up with fixed speed and fixed duplex-setting.
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|
|
More information: doc/device-tree-bindings/net/fixed-link.txt
|
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|
|
2019-06-18 01:37:17 +00:00
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|
|
config PHY_NCSI
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|
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|
|
bool "NC-SI based PHY"
|
|
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|
|
depends on DM_ETH
|
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|
|
|
2017-02-07 03:17:34 +00:00
|
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|
endif #PHYLIB
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