2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2010-10-12 11:01:40 +00:00
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/*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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* Contributor: Mahavir Jain <mjain@marvell.com>
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*/
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#include <common.h>
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2019-12-28 17:45:01 +00:00
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#include <cpu_func.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2019-11-14 19:57:30 +00:00
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#include <time.h>
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2011-10-18 14:20:48 +00:00
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#include <asm/arch/cpu.h>
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2010-10-12 11:01:40 +00:00
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#include <asm/arch/armada100.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2010-10-12 11:01:40 +00:00
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/*
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* Timer registers
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* Refer Section A.6 in Datasheet
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*/
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struct armd1tmr_registers {
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u32 clk_ctrl; /* Timer clk control reg */
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u32 match[9]; /* Timer match registers */
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u32 count[3]; /* Timer count registers */
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u32 status[3];
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u32 ie[3];
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u32 preload[3]; /* Timer preload value */
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u32 preload_ctrl[3];
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u32 wdt_match_en;
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u32 wdt_match_r;
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u32 wdt_val;
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u32 wdt_sts;
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u32 icr[3];
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u32 wdt_icr;
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u32 cer; /* Timer count enable reg */
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u32 cmr;
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u32 ilr[3];
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u32 wcr;
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u32 wfar;
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u32 wsar;
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u32 cvwr;
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};
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#define TIMER 0 /* Use TIMER 0 */
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/* Each timer has 3 match registers */
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#define MATCH_CMP(x) ((3 * TIMER) + x)
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#define TIMER_LOAD_VAL 0xffffffff
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#define COUNT_RD_REQ 0x1
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DECLARE_GLOBAL_DATA_PTR;
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2012-12-13 20:48:34 +00:00
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/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
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2010-10-12 11:01:40 +00:00
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/* For preventing risk of instability in reading counter value,
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* first set read request to register cvwr and then read same
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* register after it captures counter value.
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*/
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ulong read_timer(void)
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{
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struct armd1tmr_registers *armd1timers =
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(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
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volatile int loop=100;
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writel(COUNT_RD_REQ, &armd1timers->cvwr);
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while (loop--);
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return(readl(&armd1timers->cvwr));
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}
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2018-10-05 09:33:52 +00:00
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static ulong get_timer_masked(void)
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2010-10-12 11:01:40 +00:00
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{
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ulong now = read_timer();
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2012-12-13 20:48:34 +00:00
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if (now >= gd->arch.tbl) {
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2010-10-12 11:01:40 +00:00
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/* normal mode */
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2012-12-13 20:48:34 +00:00
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gd->arch.tbu += now - gd->arch.tbl;
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2010-10-12 11:01:40 +00:00
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} else {
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/* we have an overflow ... */
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2012-12-13 20:48:34 +00:00
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gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
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2010-10-12 11:01:40 +00:00
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}
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2012-12-13 20:48:34 +00:00
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gd->arch.tbl = now;
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2010-10-12 11:01:40 +00:00
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2012-12-13 20:48:33 +00:00
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return gd->arch.tbu;
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2010-10-12 11:01:40 +00:00
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}
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ulong get_timer(ulong base)
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{
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return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
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base);
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}
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void __udelay(unsigned long usec)
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{
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ulong delayticks;
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ulong endtime;
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delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
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endtime = get_timer_masked() + delayticks;
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while (get_timer_masked() < endtime);
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}
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/*
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* init the Timer
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*/
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int timer_init(void)
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{
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struct armd1apb1_registers *apb1clkres =
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(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
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struct armd1tmr_registers *armd1timers =
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(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
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/* Enable Timer clock at 3.25 MHZ */
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writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
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/* load value into timer */
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writel(0x0, &armd1timers->clk_ctrl);
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/* Use Timer 0 Match Resiger 0 */
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writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
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/* Preload value is 0 */
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writel(0x0, &armd1timers->preload[TIMER]);
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/* Enable match comparator 0 for Timer 0 */
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writel(0x1, &armd1timers->preload_ctrl[TIMER]);
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/* Enable timer 0 */
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writel(0x1, &armd1timers->cer);
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2012-12-13 20:48:34 +00:00
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/* init the gd->arch.tbu and gd->arch.tbl value */
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gd->arch.tbl = read_timer();
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2012-12-13 20:48:33 +00:00
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gd->arch.tbu = 0;
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2010-10-12 11:01:40 +00:00
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return 0;
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}
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#define MPMU_APRR_WDTR (1<<4)
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#define TMR_WFAR 0xbaba /* WDT Register First key */
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#define TMP_WSAR 0xeb10 /* WDT Register Second key */
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/*
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* This function uses internal Watchdog Timer
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* based reset mechanism.
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* Steps to write watchdog registers (protected access)
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* 1. Write key value to TMR_WFAR reg.
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* 2. Write key value to TMP_WSAR reg.
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* 3. Perform write operation.
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*/
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2020-12-15 15:47:52 +00:00
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void reset_cpu(void)
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2010-10-12 11:01:40 +00:00
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{
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struct armd1mpmu_registers *mpmu =
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(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
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struct armd1tmr_registers *armd1timers =
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(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
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u32 val;
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/* negate hardware reset to the WDT after system reset */
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val = readl(&mpmu->aprr);
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val = val | MPMU_APRR_WDTR;
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writel(val, &mpmu->aprr);
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/* reset/enable WDT clock */
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writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
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readl(&mpmu->wdtpcr);
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writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
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readl(&mpmu->wdtpcr);
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/* clear previous WDT status */
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writel(TMR_WFAR, &armd1timers->wfar);
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writel(TMP_WSAR, &armd1timers->wsar);
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writel(0, &armd1timers->wdt_sts);
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/* set match counter */
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writel(TMR_WFAR, &armd1timers->wfar);
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writel(TMP_WSAR, &armd1timers->wsar);
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writel(0xf, &armd1timers->wdt_match_r);
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/* enable WDT reset */
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writel(TMR_WFAR, &armd1timers->wfar);
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writel(TMP_WSAR, &armd1timers->wsar);
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writel(0x3, &armd1timers->wdt_match_en);
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while(1);
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}
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2012-02-08 08:45:53 +00:00
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On ARM it just returns the timer value.
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*/
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unsigned long long get_ticks(void)
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{
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return get_timer(0);
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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*/
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2019-12-28 17:44:59 +00:00
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ulong get_tbclk(void)
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2012-02-08 08:45:53 +00:00
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{
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return (ulong)CONFIG_SYS_HZ;
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}
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