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u-boot/drivers/pci/pci_auto_old.c

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
// SPDX-License-Identifier: GPL-2.0+
Initial revision
2002-11-03 00:24:07 +00:00
/*
dm: pci: Mark legacy files as such We don't want people changing the legacy PCI files while migration is in progress. Update the file headers to indicate that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:46 +00:00
* PCI autoconfiguration library (legacy version, do not change)
Initial revision
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*
* Author: Matt Porter <mporter@mvista.com>
*
* Copyright 2000 MontaVista Software Inc.
*/
#include <common.h>
x86: Access the VGA ROM when needed Add code to the generic pci_rom file to access the VGA ROM in PCI space when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-15 04:37:04 +00:00
#include <errno.h>
Initial revision
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#include <pci.h>
dm: pci: Mark legacy files as such We don't want people changing the legacy PCI files while migration is in progress. Update the file headers to indicate that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-29 20:17:46 +00:00
/*
* Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
* and change pci_auto.c.
*/
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-31 13:21:46 +00:00
#endif
Initial revision
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/*
*
*/
void pciauto_setup_device(struct pci_controller *hose,
pci_dev_t dev, int bars_num,
struct pci_region *mem,
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
struct pci_region *prefetch,
Initial revision
2002-11-03 00:24:07 +00:00
struct pci_region *io)
{
pci: fix some warnings related to assumptions about The following commit introduced some warnings associated with using pci_addr_t instead of a proper 32-bit data type. commit af778c6d9e2b945ee03cbc53bb976238a3374f33 Author: Andrew Sharp <andywyse6@gmail.com> Date: Wed Aug 1 12:27:16 2012 +0000 pci: fix errant data types and corresponding access functions On some platforms pci_addr_t is defined as a 64-bit data type so its not proper to use with pci_{read,write}_config_dword. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2012-09-19 04:47:36 +00:00
u32 bar_response;
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
pci_size_t bar_size;
pci: fix errant data types and corresponding access functions In a couple of places, unsigned int and pci_config_*_dword were being used when u16 and _word should be used. Unsigned int was also being used in a couple of places that should be pci_addr_t. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-01 12:27:16 +00:00
u16 cmdstat = 0;
Initial revision
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int bar, bar_nr = 0;
pci: Fix up code for CONFIG_PCI_ENUM_ONLY This option is not used by any board but appears to still be useful, at least for testing. With recent commits it does not build, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:34 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-08 05:06:40 +00:00
u8 header_type;
int rom_addr;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
pci_addr_t bar_value;
struct pci_region *bar_res;
Initial revision
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int found_mem64 = 0;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
pci: Set PCI_COMMAND_IO bit for VGA device PCI_COMMAND_IO bit must be set for VGA device as it needs to respond to legacy VGA IO address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-01 07:35:59 +00:00
u16 class;
Initial revision
2002-11-03 00:24:07 +00:00
pci: fix errant data types and corresponding access functions In a couple of places, unsigned int and pci_config_*_dword were being used when u16 and _word should be used. Unsigned int was also being used in a couple of places that should be pci_addr_t. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-01 12:27:16 +00:00
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
Initial revision
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cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
for (bar = PCI_BASE_ADDRESS_0;
bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
Initial revision
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/* Tickle the BAR and get the response */
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
Initial revision
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pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
Initial revision
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pci_hose_read_config_dword(hose, dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
continue;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
Initial revision
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found_mem64 = 0;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
Initial revision
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/* Check the BAR type and set our address mask */
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
Fix bug for io_bar size during pci scan During the pci scan process, Some devices return bar_reponse with the highest bytes 0, such as the pci bridge in uli1575 return bar_response with 0xffffff, So the bar_size should be manually set under 64K. Signed-off-by: Jason Jin <jason.jin@freescale.com>
2006-06-27 10:12:02 +00:00
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
Initial revision
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bar_res = io;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
Initial revision
2002-11-03 00:24:07 +00:00
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
bar_nr, (unsigned long long)bar_size);
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
} else {
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
PCI_BASE_ADDRESS_MEM_TYPE_64) {
u32 bar_response_upper;
u64 bar64;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
pci_hose_write_config_dword(hose, dev, bar + 4,
0xffffffff);
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
pci_hose_read_config_dword(hose, dev, bar + 4,
&bar_response_upper);
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
bar64 = ((u64)bar_response_upper << 32) | bar_response;
Initial revision
2002-11-03 00:24:07 +00:00
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
found_mem64 = 1;
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
} else {
bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
}
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
bar_res = prefetch;
else
bar_res = mem;
Initial revision
2002-11-03 00:24:07 +00:00
pci: Indicate prefetchable memory allocate when debugging At present the PCI output displays 'Mem' when it allocates memory for a PCI device, whether it is prefetchable or not. There is a distinction since the memory comes from separate pools. Use 'Prf' instead of 'Mem' when allocating prefetchable memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-27 21:47:18 +00:00
debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
bar_nr, bar_res == prefetch ? "Prf" : "Mem",
(unsigned long long)bar_size);
drivers/pci: Fix for debug builds without CONFIG_PCI_ENUM_ONLY The debug printing references bar_res, which exists only if CONFIG_PCI_ENUM_ONLY is not defined. Therefore move it into the ifdef'd area. Signed-off-by: Phil Sutter <phil@nwl.cc> Acked-by: Stefan Roese <sr@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2015-12-25 13:41:17 +00:00
#endif
Initial revision
2002-11-03 00:24:07 +00:00
}
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
Initial revision
2002-11-03 00:24:07 +00:00
/* Write it out and update our limit */
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
Initial revision
2002-11-03 00:24:07 +00:00
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (found_mem64) {
Initial revision
2002-11-03 00:24:07 +00:00
bar += 4;
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
#else
/*
* If we are a 64-bit decoder then increment to the
* upper 32 bits of the bar and force it to locate
* in the lower 4GB of memory.
*/
Initial revision
2002-11-03 00:24:07 +00:00
pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
pci: Allow for PCI addresses to be 64-bit PCI bus is inherently 64-bit. While not all system require access to the full 64-bit PCI address range some do. This allows those systems to enable the full PCI address width via CONFIG_SYS_PCI_64BIT. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com> Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-21 13:36:08 +00:00
#endif
Initial revision
2002-11-03 00:24:07 +00:00
}
}
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
#endif
cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
Initial revision
2002-11-03 00:24:07 +00:00
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("\n");
Initial revision
2002-11-03 00:24:07 +00:00
bar_nr++;
}
pci: Fix up code for CONFIG_PCI_ENUM_ONLY This option is not used by any board but appears to still be useful, at least for testing. With recent commits it does not build, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:34 +00:00
#ifndef CONFIG_PCI_ENUM_ONLY
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-08 05:06:40 +00:00
/* Configure the expansion ROM address */
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
pci: Fix expansion ROM programming for multi-function devices PCI_HEADER_TYPE register (offset 0x0e) bit 7 is an indicator for multi-function devices. We should mask it off before using it as the header type. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-07 09:13:18 +00:00
header_type &= 0x7f;
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-08 05:06:40 +00:00
if (header_type != PCI_HEADER_TYPE_CARDBUS) {
rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
pci_hose_write_config_dword(hose, dev, rom_addr, 0xfffffffe);
pci_hose_read_config_dword(hose, dev, rom_addr, &bar_response);
if (bar_response) {
bar_size = -(bar_response & ~1);
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI Autoconfig: ROM, size=%#x, ",
(unsigned int)bar_size);
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-08 05:06:40 +00:00
if (pciauto_region_allocate(mem, bar_size,
&bar_value) == 0) {
pci_hose_write_config_dword(hose, dev, rom_addr,
bar_value);
}
cmdstat |= PCI_COMMAND_MEMORY;
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("\n");
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-08 05:06:40 +00:00
}
}
pci: Fix up code for CONFIG_PCI_ENUM_ONLY This option is not used by any board but appears to still be useful, at least for testing. With recent commits it does not build, so fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:34 +00:00
#endif
pci: Configure expansion ROM during auto config process Currently PCI expansion ROM address is assigned by a call to pciauto_setup_rom() outside of the pci auto config process. This does not work when expansion ROM is on a device behind PCI bridge where bridge's memory limit register was already programmed to a value that does not cover the newly assigned expansion ROM address. To fix this, we should configure the ROM address during the auto config process. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
2015-07-08 05:06:40 +00:00
pci: Set PCI_COMMAND_IO bit for VGA device PCI_COMMAND_IO bit must be set for VGA device as it needs to respond to legacy VGA IO address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-10-01 07:35:59 +00:00
/* PCI_COMMAND_IO must be set for VGA device */
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
if (class == PCI_CLASS_DISPLAY_VGA)
cmdstat |= PCI_COMMAND_IO;
pci: fix errant data types and corresponding access functions In a couple of places, unsigned int and pci_config_*_dword were being used when u16 and _word should be used. Unsigned int was also being used in a couple of places that should be pci_addr_t. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-01 12:27:16 +00:00
pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-31 13:21:46 +00:00
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-16 13:01:15 +00:00
CONFIG_SYS_PCI_CACHE_LINE_SIZE);
Initial revision
2002-11-03 00:24:07 +00:00
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
}
Minor improvements to drivers/pci_auto.c - Make pciauto_{pre,post}scan_setup_bridge non-static - Added physical address display in debug messages. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-07-11 19:51:48 +00:00
void pciauto_prescan_setup_bridge(struct pci_controller *hose,
Initial revision
2002-11-03 00:24:07 +00:00
pci_dev_t dev, int sub_bus)
{
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
PCI: add 64-bit prefetchable memory support PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-02 08:53:13 +00:00
u16 cmdstat, prefechable_64;
Initial revision
2002-11-03 00:24:07 +00:00
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
pci: fix errant data types and corresponding access functions In a couple of places, unsigned int and pci_config_*_dword were being used when u16 and _word should be used. Unsigned int was also being used in a couple of places that should be pci_addr_t. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-01 12:27:16 +00:00
pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
PCI: add 64-bit prefetchable memory support PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-02 08:53:13 +00:00
pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
&prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
Initial revision
2002-11-03 00:24:07 +00:00
/* Configure bus number registers */
pciauto setup bridge The P2P bridge bus numbers programmed into the device are relative to hose->first_busno. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-07-11 19:52:08 +00:00
pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
PCI_BUS(dev) - hose->first_busno);
pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
sub_bus - hose->first_busno);
Initial revision
2002-11-03 00:24:07 +00:00
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (pci_mem) {
Initial revision
2002-11-03 00:24:07 +00:00
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
(pci_mem->bus_lower & 0xfff00000) >> 16);
cmdstat |= PCI_COMMAND_MEMORY;
}
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
if (pci_prefetch) {
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
/* Set up memory and I/O filter limits, assume 32-bit I/O space */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
(pci_prefetch->bus_lower & 0xfff00000) >> 16);
PCI: add 64-bit prefetchable memory support PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-02 08:53:13 +00:00
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev,
PCI_PREF_BASE_UPPER32,
pci_prefetch->bus_lower >> 32);
#else
pci_hose_write_config_dword(hose, dev,
PCI_PREF_BASE_UPPER32,
0x0);
#endif
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
cmdstat |= PCI_COMMAND_MEMORY;
} else {
/* We don't support prefetchable memory for now, so disable */
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
* Made sure the code which disables prefetch for PCI devices sets the size of the prefetch region to 0 Patch by Andy Fleming on 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
2006-06-28 15:44:23 +00:00
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
PCI: add 64-bit prefetchable memory support PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-02 08:53:13 +00:00
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
}
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
}
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (pci_io) {
Initial revision
2002-11-03 00:24:07 +00:00
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
(pci_io->bus_lower & 0x0000f000) >> 8);
pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
(pci_io->bus_lower & 0xffff0000) >> 16);
cmdstat |= PCI_COMMAND_IO;
}
/* Enable memory and I/O accesses, enable bus master */
pci: fix errant data types and corresponding access functions In a couple of places, unsigned int and pci_config_*_dword were being used when u16 and _word should be used. Unsigned int was also being used in a couple of places that should be pci_addr_t. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-01 12:27:16 +00:00
pci_hose_write_config_word(hose, dev, PCI_COMMAND,
cmdstat | PCI_COMMAND_MASTER);
Initial revision
2002-11-03 00:24:07 +00:00
}
Minor improvements to drivers/pci_auto.c - Make pciauto_{pre,post}scan_setup_bridge non-static - Added physical address display in debug messages. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-07-11 19:51:48 +00:00
void pciauto_postscan_setup_bridge(struct pci_controller *hose,
Initial revision
2002-11-03 00:24:07 +00:00
pci_dev_t dev, int sub_bus)
{
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
Initial revision
2002-11-03 00:24:07 +00:00
/* Configure bus number registers */
pciauto setup bridge The P2P bridge bus numbers programmed into the device are relative to hose->first_busno. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2007-07-11 19:52:08 +00:00
pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
sub_bus - hose->first_busno);
Initial revision
2002-11-03 00:24:07 +00:00
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (pci_mem) {
Initial revision
2002-11-03 00:24:07 +00:00
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_mem, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
(pci_mem->bus_lower - 1) >> 16);
Initial revision
2002-11-03 00:24:07 +00:00
}
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
if (pci_prefetch) {
PCI: add 64-bit prefetchable memory support PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-02 08:53:13 +00:00
u16 prefechable_64;
pci_hose_read_config_word(hose, dev,
PCI_PREF_MEMORY_LIMIT,
&prefechable_64);
prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
/* Round memory allocator to 1MB boundary */
pciauto_region_align(pci_prefetch, 0x100000);
pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
(pci_prefetch->bus_lower - 1) >> 16);
PCI: add 64-bit prefetchable memory support PCI specification allow prefetchable memory to be 32-bit or 64-bit. PCI express specification states that all memmory bars for prefetchable memory must be implemented as 64-bit. They all require that 64 bit prefetchble memory are suported especially when u-boot is ported to more and more 64bit processors. Signed-off-by: David Feng <fenghua@phytium.com.cn> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-02-02 08:53:13 +00:00
if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
#ifdef CONFIG_SYS_PCI_64BIT
pci_hose_write_config_dword(hose, dev,
PCI_PREF_LIMIT_UPPER32,
(pci_prefetch->bus_lower - 1) >> 32);
#else
pci_hose_write_config_dword(hose, dev,
PCI_PREF_LIMIT_UPPER32,
0x0);
#endif
Added support for PCI prefetchable region and BARs If a host controller sets up a region as prefetchable and a device's BAR denotes it as prefetchable, allocate the BAR into the prefetch region. If a BAR is prefetchable and no prefetchable region has been setup by the controller we fall back to allocating the BAR into the normally memory region. Patch by Kumar Gala 11 Jan 2006
2006-01-11 19:24:15 +00:00
}
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
if (pci_io) {
Initial revision
2002-11-03 00:24:07 +00:00
/* Round I/O allocator to 4KB boundary */
pciauto_region_align(pci_io, 0x1000);
pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
Initial revision
2002-11-03 00:24:07 +00:00
pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
Initial revision
2002-11-03 00:24:07 +00:00
}
}
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
/*
* HJF: Changed this to return int. I think this is required
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined.
2002-11-19 11:04:11 +00:00
* to get the correct result when scanning bridges
*/
int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
Initial revision
2002-11-03 00:24:07 +00:00
{
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
struct pci_region *pci_mem;
struct pci_region *pci_prefetch;
struct pci_region *pci_io;
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined.
2002-11-19 11:04:11 +00:00
unsigned int sub_bus = PCI_BUS(dev);
Initial revision
2002-11-03 00:24:07 +00:00
unsigned short class;
* Patch by Yuli Barcohen, 26 Jan 2004: Allow bzip2 compression for small memory footprint boards * Patch by Brad Kemp, 21 Jan 2004: Add support for CFI flash driver for both the Intel and the AMD command sets. * Patch by Travis Sawyer, 20 Jan 2004: Fix pci bridge auto enumeration of sibling p2p bridges. * Patch by Tolunay Orkun, 12 Jan 2004: Add some delays as needed for Intel LXT971A PHY support * Patches by Stephan Linz, 09 Jan 2004: - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c - make DK1C20 board configuration related to ASMI conform to documentation
2004-02-08 22:55:38 +00:00
int n;
Initial revision
2002-11-03 00:24:07 +00:00
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
pci_mem = hose->pci_mem;
pci_prefetch = hose->pci_prefetch;
pci_io = hose->pci_io;
Initial revision
2002-11-03 00:24:07 +00:00
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
switch (class) {
Initial revision
2002-11-03 00:24:07 +00:00
case PCI_CLASS_BRIDGE_PCI:
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI Autoconfig: Found P2P bridge, device %d\n",
PCI_DEV(dev));
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:25 +00:00
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
pciauto_setup_device(hose, dev, 2, pci_mem,
pci_prefetch, pci_io);
Initial revision
2002-11-03 00:24:07 +00:00
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
/* Passing in current_busno allows for sibling P2P bridges */
dm: pci: Add a uclass for PCI Add a uclass for PCI controllers and a generic one for PCI devices. Adjust the 'pci' command and the existing PCI support to work with this new uclass. Keep most of the compatibility code in a separate file so that it can be removed one day. TODO: Add more header file comments to the new parts of pci.h Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:25 +00:00
hose->current_busno++;
* Patch by Yuli Barcohen, 26 Jan 2004: Allow bzip2 compression for small memory footprint boards * Patch by Brad Kemp, 21 Jan 2004: Add support for CFI flash driver for both the Intel and the AMD command sets. * Patch by Travis Sawyer, 20 Jan 2004: Fix pci bridge auto enumeration of sibling p2p bridges. * Patch by Tolunay Orkun, 12 Jan 2004: Add some delays as needed for Intel LXT971A PHY support * Patches by Stephan Linz, 09 Jan 2004: - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c - make DK1C20 board configuration related to ASMI conform to documentation
2004-02-08 22:55:38 +00:00
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
* Patch by Jian Zhang, 3 Feb 2004: - Changed the incorrect FAT12BUFSIZE - data_begin in fsdata can be negative. Changed it to be short. * Code cleanup
2004-02-10 00:03:41 +00:00
/*
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
* need to figure out if this is a subordinate bridge on the bus
* Patch by Yuli Barcohen, 26 Jan 2004: Allow bzip2 compression for small memory footprint boards * Patch by Brad Kemp, 21 Jan 2004: Add support for CFI flash driver for both the Intel and the AMD command sets. * Patch by Travis Sawyer, 20 Jan 2004: Fix pci bridge auto enumeration of sibling p2p bridges. * Patch by Tolunay Orkun, 12 Jan 2004: Add some delays as needed for Intel LXT971A PHY support * Patches by Stephan Linz, 09 Jan 2004: - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c - make DK1C20 board configuration related to ASMI conform to documentation
2004-02-08 22:55:38 +00:00
* to be able to properly set the pri/sec/sub bridge registers.
*/
n = pci_hose_scan_bus(hose, hose->current_busno);
* Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c
2004-02-22 23:46:08 +00:00
/* figure out the deepest we've gone for this leg */
linux/kernel.h: sync min, max, min3, max3 macros with Linux U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
2014-11-06 18:03:31 +00:00
sub_bus = max((unsigned int)n, sub_bus);
* Patch by Rune Torgersen, 13 Feb 2003: Add support for Motorola MPC8266ADS board * Patch by Kyle Harris, 19 Feb 2003: patches for the Intel lubbock board: memsetup.S - general cleanup (based on Robert's csb226 code) flash.c - overhaul, actually works now lubbock.c - fix init funcs to return proper value * Patch by Kenneth Johansson, 26 Feb 2003: - Fixed off by one in RFTA calculation. - No need to abort when LDF is lower than we can program it's only minimum timing so clamp it to what we can do. - Takes function pointer to function for reading the spd_nvram. Usefull for faking data or hardcode a module without the nvram. - fix other user for above change - fix some comments. * Patches by Brian Waite, 26 Feb 2003: - fix port for evb64260 board - fix PCI for evb64260 board - fix PCI scan * Patch by Reinhard Meyer, 1 Mar 2003: Add support for EMK TOP860 Module * Patch by Yuli Barcohen, 02 Mar 2003: Add SPD EEPROM support for MPC8260ADS board
2003-03-06 00:58:30 +00:00
pciauto_postscan_setup_bridge(hose, dev, sub_bus);
* Patch by Yuli Barcohen, 26 Jan 2004: Allow bzip2 compression for small memory footprint boards * Patch by Brad Kemp, 21 Jan 2004: Add support for CFI flash driver for both the Intel and the AMD command sets. * Patch by Travis Sawyer, 20 Jan 2004: Fix pci bridge auto enumeration of sibling p2p bridges. * Patch by Tolunay Orkun, 12 Jan 2004: Add some delays as needed for Intel LXT971A PHY support * Patches by Stephan Linz, 09 Jan 2004: - avoid warning: unused variable `piop' in board/altera/common/sevenseg.c - make DK1C20 board configuration related to ASMI conform to documentation
2004-02-08 22:55:38 +00:00
* Patch by Rune Torgersen, 13 Feb 2003: Add support for Motorola MPC8266ADS board * Patch by Kyle Harris, 19 Feb 2003: patches for the Intel lubbock board: memsetup.S - general cleanup (based on Robert's csb226 code) flash.c - overhaul, actually works now lubbock.c - fix init funcs to return proper value * Patch by Kenneth Johansson, 26 Feb 2003: - Fixed off by one in RFTA calculation. - No need to abort when LDF is lower than we can program it's only minimum timing so clamp it to what we can do. - Takes function pointer to function for reading the spd_nvram. Usefull for faking data or hardcode a module without the nvram. - fix other user for above change - fix some comments. * Patches by Brian Waite, 26 Feb 2003: - fix port for evb64260 board - fix PCI for evb64260 board - fix PCI scan * Patch by Reinhard Meyer, 1 Mar 2003: Add support for EMK TOP860 Module * Patch by Yuli Barcohen, 02 Mar 2003: Add SPD EEPROM support for MPC8260ADS board
2003-03-06 00:58:30 +00:00
sub_bus = hose->current_busno;
Initial revision
2002-11-03 00:24:07 +00:00
break;
* Patches by David Mller, 31 Jan 2003: - minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 * Patch by Reinhard Meyer, 5 Feb 2003: fix PLPRCR/SCCR init sequence on 8xx to allow for changes of EBDF by software * Patch by Vladimir Gurevich, 07 Feb 2003: "API-compatibility patch" for 4xx I2C driver
2003-03-06 21:55:29 +00:00
case PCI_CLASS_BRIDGE_CARDBUS:
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
/*
* just do a minimal setup of the bridge,
* let the OS take care of the rest
*/
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
pciauto_setup_device(hose, dev, 0, pci_mem,
pci_prefetch, pci_io);
* Patches by David Mller, 31 Jan 2003: - minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 * Patch by Reinhard Meyer, 5 Feb 2003: fix PLPRCR/SCCR init sequence on 8xx to allow for changes of EBDF by software * Patch by Vladimir Gurevich, 07 Feb 2003: "API-compatibility patch" for 4xx I2C driver
2003-03-06 21:55:29 +00:00
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
PCI_DEV(dev));
* Patches by David Mller, 31 Jan 2003: - minimal setup for CardBus bridges - add EEPROM read/write support in the CS8900 driver - add support for the builtin I2C controller in the Samsung s3c24x0 chips - add support for MPL's VCMA9 (Samsung s3c2410 based) board * Patch by Steven Scholz, 04 Feb 2003: add support for RTC DS1307 * Patch by Reinhard Meyer, 5 Feb 2003: fix PLPRCR/SCCR init sequence on 8xx to allow for changes of EBDF by software * Patch by Vladimir Gurevich, 07 Feb 2003: "API-compatibility patch" for 4xx I2C driver
2003-03-06 21:55:29 +00:00
hose->current_busno++;
break;
Update CONFIG_PCIAUTO_SKIP_HOST_BRIDGE to related boards Remove test for CONFIG_MPC5200 in drivers/pci/pci_auto.c and define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE in related board configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
2008-03-30 06:19:06 +00:00
#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
* Make Ethernet autonegotiation on INCA-IP work for all clock rates; allow selection of clock frequency as "make" target * Implement memory autosizing code for IceCube boards * Configure network port on INCA-IP for autonegotiation * Fix overflow problem in network timeout code * Patch by Richard Woodruff, 8 Aug 2003: Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
2003-08-17 18:55:18 +00:00
case PCI_CLASS_BRIDGE_OTHER:
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI Autoconfig: Skipping bridge device %d\n",
PCI_DEV(dev));
* Make Ethernet autonegotiation on INCA-IP work for all clock rates; allow selection of clock frequency as "make" target * Implement memory autosizing code for IceCube boards * Configure network port on INCA-IP for autonegotiation * Fix overflow problem in network timeout code * Patch by Richard Woodruff, 8 Aug 2003: Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
2003-08-17 18:55:18 +00:00
break;
#endif
mpc83xx: Add esd VME8349 board support This patch adds support for the esd VME8349 board equipped with the MPC8349. It's a VME PMC carrier board equipped with the Tundra TSI148 VME-bridge. Signed-off-by: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-07-25 04:19:12 +00:00
#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
Add PCI support for the TQM834x board.
2005-10-17 00:39:53 +00:00
case PCI_CLASS_BRIDGE_OTHER:
/*
* The host/PCI bridge 1 seems broken in 8349 - it presents
* itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
* device claiming resources io/mem/irq.. we only allow for
* the PIMMR window to be allocated (BAR0 - 1MB size)
*/
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
pci: clean up some whitespace and formatting I tried to clean up the white space and formatting offenses and inconsistencies in the generic PCI code that obviously has been around for some time. Emphasis on large increases in readability and maintainability and consistency. I omitted the platform/processor specific files in the drivers/pci directory because I wanted to leave those file to those that care more about them. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:29 +00:00
pciauto_setup_device(hose, dev, 0, hose->pci_mem,
hose->pci_prefetch, hose->pci_io);
Add PCI support for the TQM834x board.
2005-10-17 00:39:53 +00:00
break;
#endif
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
pci: Use debug() instead of DEBUGF() in pci_auto.c This file does not need its own way of doing debug(). Clean it up to use the new way. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-31 15:31:33 +00:00
debug("PCI AutoConfig: Found PowerPC device\n");
pci: add CONFIG_PCI_ENUM_ONLY for platforms that don't need PCI setup done Introduce CONFIG_PCI_ENUM_ONLY variable for platforms that just want a quick enumberation of the PCI devices, but don't need any setup work done. This is very beneficial on platforms that have u-boot loaded by another boot loader which does a more sophisticated job of setup of PCI devices than u-boot. That way, u-boot can just read what's there and get on with life. This is what SeaBIOS does. Signed-off-by: Andrew Sharp <andywyse6@gmail.com>
2012-08-29 14:16:32 +00:00
Initial revision
2002-11-03 00:24:07 +00:00
default:
dm: pci: Support bridge device configuration correctly Commit aec241d "dm: pci: Use the correct hose when configuring devices" was an attempt to fix pci bridge device configuration, but unfortunately that does not work 100%. In pciauto_config_devices(), the fix tried to call pciauto_config_device() with a ctlr_hose which is supposed to be the root controller hose, however when walking through a pci topology with 2 or more pci bridges this logic simply fails. The call chain is: pciauto_config_devices()->pciauto_config_device() ->dm_pci_hose_probe_bus(). Here the call to dm_pci_hose_probe_bus() does not make any sense as the given hose is not the bridge device's hose, instead it is either the root controller's hose (case#1: if it is the 2nd pci bridge), or the bridge's parent bridge's hose (case#2: if it is the 3rd pci bridge). In both cases the logic is wrong. For example, for failing case#1 if the bridge device to config has the same devfn as one of the devices under the root controller, the call to pci_bus_find_devfn() will return the udevice of that pci device under the root controller as the bus, but this is wrong as the udevice is not a bus which does not contain all the necessary bits associated with the udevice which causes further failures. To correctly support pci bridge device configuration, we should still call pciauto_config_device() with the pci bridge's hose directly. In order to access valid pci region information, we need to refer to the root controller simply by a call to pci_bus_to_hose(0) and get the region information there in the pciauto_prescan_setup_bridge(), pciauto_postscan_setup_bridge() and pciauto_config_device(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-18 16:20:06 +00:00
pciauto_setup_device(hose, dev, 6, pci_mem,
pci_prefetch, pci_io);
Initial revision
2002-11-03 00:24:07 +00:00
break;
}
* Patch by Thomas Frieden, 13 Nov 2002: Add code for AmigaOne board (preliminary merge to U-Boot, still WIP) * Patch by Jon Diekema, 12 Nov 2002: - Adding URL for IEEE OUI lookup - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED being defined. - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and root-on-nfs macros are designed to switch how the default boot method gets defined.
2002-11-19 11:04:11 +00:00
return sub_bus;
Initial revision
2002-11-03 00:24:07 +00:00
}
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