mirror of
https://github.com/AsahiLinux/u-boot
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* Patch by Yuli Barcohen, 26 Jan 2004:
Allow bzip2 compression for small memory footprint boards
* Patch by Brad Kemp, 21 Jan 2004:
Add support for CFI flash driver for both the Intel and the AMD
command sets.
* Patch by Travis Sawyer, 20 Jan 2004:
Fix pci bridge auto enumeration of sibling p2p bridges.
* Patch by Tolunay Orkun, 12 Jan 2004:
Add some delays as needed for Intel LXT971A PHY support
* Patches by Stephan Linz, 09 Jan 2004:
- avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
- make DK1C20 board configuration related to ASMI conform to
documentation
This commit is contained in:
wdenk
parent
f6e20fc6ca
commit
5653fc335a
11 changed files with 1083 additions and 14 deletions
18
CHANGELOG
18
CHANGELOG
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@ -2,6 +2,24 @@
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Changes since U-Boot 1.0.1:
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======================================================================
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* Patch by Yuli Barcohen, 26 Jan 2004:
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Allow bzip2 compression for small memory footprint boards
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* Patch by Brad Kemp, 21 Jan 2004:
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Add support for CFI flash driver for both the Intel and the AMD
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command sets.
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* Patch by Travis Sawyer, 20 Jan 2004:
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Fix pci bridge auto enumeration of sibling p2p bridges.
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* Patch by Tolunay Orkun, 12 Jan 2004:
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Add some delays as needed for Intel LXT971A PHY support
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* Patches by Stephan Linz, 09 Jan 2004:
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- avoid warning: unused variable `piop' in board/altera/common/sevenseg.c
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- make DK1C20 board configuration related to ASMI conform to
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documentation
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* Patch by Anders Larsen, 09 Jan 2004:
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ARM memory layout fixes: the abort-stack is now set up in the
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6
README
6
README
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@ -1643,7 +1643,11 @@ Configuration Settings:
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- CFG_FLASH_CFI:
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Define if the flash driver uses extra elements in the
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common flash structure for storing flash geometry
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common flash structure for storing flash geometry.
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- CFG_FLASH_CFI_DRIVER
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This option also enables the building of the cfi_flash driver
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in the drivers directory
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- CFG_RX_ETH_BUFFER:
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Defines the number of ethernet receive buffers. On some
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@ -44,7 +44,7 @@ static int sevenseg_init_done = 0;
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static inline void __sevenseg_set_masked (unsigned int mask, int value)
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{
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nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
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nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
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#ifdef SEVENSEG_WRONLY /* emulate read access */
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@ -97,7 +97,7 @@ static inline void __sevenseg_toggle_masked (unsigned int mask)
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static inline void __sevenseg_set (unsigned int value)
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{
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nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
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nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
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#ifdef SEVENSEG_WRONLY /* emulate read access */
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@ -126,7 +126,7 @@ static inline void __sevenseg_set (unsigned int value)
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static inline void __sevenseg_init (void)
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{
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nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
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nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
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__sevenseg_set(0);
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@ -333,8 +333,14 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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#ifdef CONFIG_BZIP2
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case IH_COMP_BZIP2:
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printf (" Uncompressing %s ... ", name);
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/*
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* If we've got less than 4 MB of malloc() space,
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* use slower decompression algorithm which requires
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* at most 2300 KB of memory.
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*/
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i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load),
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&unc_len, (char *)data, len, 0, 0);
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&unc_len, (char *)data, len,
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CFG_MALLOC_LEN < (4096 * 1024), 0);
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if (i != BZ_OK) {
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printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
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SHOW_BOOT_PROGRESS (-6);
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@ -99,7 +99,9 @@ int miiphy_reset (unsigned char addr)
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#endif
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return (-1);
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}
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#ifdef CONFIG_PHY_RESET_DELAY
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udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
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#endif
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/*
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* Poll the control register for the reset bit to go to 0 (it is
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* auto-clearing). This should happen within 0.5 seconds per the
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@ -113,6 +113,9 @@ int miiphy_read (unsigned char addr, unsigned char reg,
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printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */
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#endif
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#ifdef CONFIG_PHY_CMD_DELAY
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udelay (CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */
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#endif
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sta_reg = in32 (EMAC_STACR);
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i = 0;
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while ((sta_reg & EMAC_STACR_OC) == 0) {
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@ -173,6 +176,9 @@ int miiphy_write (unsigned char addr, unsigned char reg,
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out32 (EMAC_STACR, sta_reg);
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#ifdef CONFIG_PHY_CMD_DELAY
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udelay (CONFIG_PHY_CMD_DELAY); /* Intel LXT971A needs this */
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#endif
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/* wait for completion */
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i = 0;
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sta_reg = in32 (EMAC_STACR);
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@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
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LIB = libdrivers.a
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OBJS = 3c589.o 5701rls.o ali512x.o \
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bcm570x.o bcm570x_autoneg.o cfb_console.o \
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bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
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cs8900.o ct69000.o dataflash.o dc2114x.o \
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e1000.o eepro100.o \
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i8042.o i82365.o inca-ip_sw.o \
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1018
drivers/cfi_flash.c
Normal file
1018
drivers/cfi_flash.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -163,7 +163,8 @@ static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
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/* Configure bus number registers */
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pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
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pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus + 1);
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/* TBS: passed in sub_bus is correct, removed the +1 */
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pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus);
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pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
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if (pci_mem)
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@ -284,6 +285,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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unsigned int sub_bus = PCI_BUS(dev);
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unsigned short class;
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unsigned char prg_iface;
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int n;
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pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
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@ -294,11 +296,19 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
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pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
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DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
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pciauto_prescan_setup_bridge(hose, dev, sub_bus);
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pci_hose_scan_bus(hose, hose->current_busno);
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/* TBS: Passing in current_busno allows for sibling P2P bridges */
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pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
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/*
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* TBS: need to figure out if this is a subordinate bridge on the bus
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* to be able to properly set the pri/sec/sub bridge registers.
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*/
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n = pci_hose_scan_bus(hose, hose->current_busno);
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/* TBS: figure out the deepest we've gone for this leg */
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sub_bus = max(n, sub_bus);
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pciauto_postscan_setup_bridge(hose, dev, sub_bus);
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sub_bus = hose->current_busno;
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break;
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@ -647,8 +647,8 @@
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* ASMI is for Cyclone devices only and only works when the configuration
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* is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
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*----------------------------------------------------------------------*/
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#define CONFIG_NIOS_ASMI /* Enable ASMI */
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#define CFG_NIOS_ASMIBASE 0x00920b00 /* ASMI base address */
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#define CONFIG_NIOS_ASMI /* Enable ASMI */
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#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
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/*------------------------------------------------------------------------
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* COMMANDS
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@ -42,7 +42,8 @@ typedef struct {
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ulong erase_blk_tout; /* maximum block erase timeout */
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ulong write_tout; /* maximum write timeout */
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ulong buffer_write_tout; /* maximum buffer write timeout */
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ushort vendor; /* the primary vendor id */
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ushort cmd_reset; /* Vendor specific reset command */
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#endif
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} flash_info_t;
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@ -61,6 +62,8 @@ typedef struct {
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#define FLASH_CFI_BY32 0x04
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#define FLASH_CFI_BY64 0x08
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/* convert between bit value and numeric value */
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#define CFI_FLASH_SHIFT_WIDTH 3
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/* Prototypes */
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extern unsigned long flash_init (void);
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@ -78,6 +81,8 @@ extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
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/* board/?/flash.c */
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#if defined(CFG_FLASH_PROTECTION)
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extern int flash_real_protect(flash_info_t *info, long sector, int prot);
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extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
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extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
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#endif /* CFG_FLASH_PROTECTION */
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/*-----------------------------------------------------------------------
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