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u-boot/drivers/reset/Makefile

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drivers: cosmetic: Convert SPDX license tags to Linux Kernel style Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-26 09:02:52 +02:00
# SPDX-License-Identifier: GPL-2.0
#
Add a reset driver framework/uclass A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 09:43:58 -06:00
# Copyright (c) 2016, NVIDIA CORPORATION.
#
obj-$(CONFIG_DM_RESET) += reset-uclass.o
reset: implement a reset test This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 09:43:59 -06:00
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
reset: Add STi reset support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-22 10:54:03 +01:00
obj-$(CONFIG_STI_RESET) += sti-reset.o
dm: reset: add stm32 reset driver This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 18:00:07 +02:00
obj-$(CONFIG_STM32_RESET) += stm32-reset.o
reset: implement a driver for the Tegra CAR Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 10:45:58 -06:00
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
reset: add Tegra186 reset driver In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 11:28:25 -06:00
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
reset: Introduce TI System Control Interface (TI SCI) reset driver Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a reset driver that communicates to the system controller over the TI SCI protocol for performing reset management of various devices present on the SoC. Various reset functionalities are achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/reset/reset-ti-sci.c driver of the Linux kernel. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-08-27 15:57:41 +05:30
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
ARC: HSDK: introduce reset driver Introduce reset driver for Synopsys ARC HSDK SoC Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-10-08 19:29:30 +03:00
obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
dm: reset: add BCM6345 reset driver This is a simplified version of linux/arch/mips/bcm63xx/reset.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-03 15:10:21 +02:00
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
reset: uniphier: add reset controller driver for UniPhier SoCs This is the initial commit for UniPhier reset controller driver. Most code was ported from Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-08 13:25:31 +09:00
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
cosmetic: reset: ast2500: Rename driver and configs 1. Rename AST2500 reset driver from ast2500-reset.c to reset-ast2500.c 2. Rename AST2500 reset kconfig option from AST2500_RESET to RESET_AST2500 Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-15 10:25:14 +08:00
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
reset: aspeed: Add AST2600 reset support Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-12-14 13:54:26 +08:00
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
reset: rockchip: implement rk3588 lookup table The current DT bindings for the rk3588 clock use a different ID than the one that is supposed to be written to the hardware registers. Thus, we cannot use directly the id provided in the phandle, but rather use a lookup table to correctly setup the hardware. This approach has been implemented already in Linux, by commit : f1c506d152ff ("clk: rockchip: add clock controller for the RK3588") Hence, implement a similar approach using the lookup table, and adapt the existing reset driver to work with SoCs using lookup table. The file rst-rk3588.c has been copied as much as possible from Linux. Adapt the clk rk3588 driver as well to bind the reset driver with the lookup table. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
2023-05-15 13:55:04 +03:00
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
reset: Add Amlogic Meson Reset Controller The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-29 14:55:25 +02:00
obj-$(CONFIG_RESET_MESON) += reset-meson.o
reset: socfpga: add reset driver for SoCFPGA platform Add a DM compatible reset driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-04 17:18:20 -05:00
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
reset: MedaiTek: add reset controller driver for MediaTek SoCs This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2018-12-20 16:12:51 +08:00
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
reset: add reset controller driver for MediaTek MIPS platform This patch adds reset controller driver for MediaTek MIPS platform and header file for mt7628. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-09-25 17:45:29 +08:00
obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
reset: Add Allwinner RESET driver Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-01-18 22:18:13 +05:30
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
reset: add reset driver for HiSilicon platform It adds a Driver Model compatible reset driver for HiSlicon platform. The driver implements a custom .of_xlate function, and uses .data field as reset register offset and .id field as bit shift. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-20 15:32:39 +08:00
obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
imx: add support for i.MX7/i.MX8MQ reset controller Add support for the reset controller that's used on the i.MX7D and i.MX8MQ. This will be needed to be able to assert the PCIe reset pins. Bindings taken from Linux, driver implementation mostly taken from Linux and adjusted to U-Boot infrastructure. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2019-10-03 16:08:35 +02:00
obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
reset: Convert ipq4019 driver to a generic Qcom driver Since the base functionality remains the same for a reset driver on Qcom SoCs, so leverage that to convert ipq4019 specific reset driver to a generic Qcom reset driver. With that one just need to provide SoC specific reset table. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-08-04 19:57:11 +05:30
obj-$(CONFIG_RESET_QCOM) += reset-qcom.o
configs: reset: fu540: enable dm reset framework for SiFive Add necessary defconfig and Kconfig entries to enable SiFive SoC's reset driver so as to utilise U-Boot's reset framework. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-29 02:36:14 -07:00
obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
reset: Add generic reset driver This patch adds a generic reset driver. It is designed to be useful when one has a register in a regmap which contains bits that reset other devices. I thought this seemed like a very generic use, so here is a generic driver. The overall structure has been modeled on the syscon-reboot driver. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-06-24 06:41:14 -04:00
obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
reset: Add Raspberry Pi 4 firmware reset controller Raspberry Pi 4's co-processor controls some of the board's HW initialization process, but it's up to Linux to trigger it when relevant. Introduce a reset controller capable of interfacing with RPi4's co-processor that models these firmware initialization routines as reset lines. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-06-29 18:37:23 +02:00
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
reset: add reset controller driver for SCMI agents This change introduces a reset controller driver for SCMI agent devices. When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent binds a reset controller device for each SCMI reset domain protocol devices enabled in the FDT. SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Reset Domain protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Cc: Simon Glass <sjg@chromium.org> Cc: Peng Fan <peng.fan@nxp.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-09-09 18:44:06 +02:00
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
reset: zynqmp: Add reset controller for ZynqMP SoC Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-30 08:00:10 +02:00
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
reset: dra7: Add a reset driver Add a reset driver to bring IPs out of reset. Signed-off-by: Keerthy <j-keerthy@ti.com> [Amjad: reset_ops structure member "free" has been renamed to "rfree", use the latter instead] Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-01-27 13:16:51 +01:00
obj-$(CONFIG_RESET_DRA7) += reset-dra7.o
reset: at91: Add reset driver for basic assert/deassert operations Add support for at91 reset controller's basic assert/deassert operations. Since this driver conflicts with the SYSRESET driver because they both bind to the same RSTC node, implement a custom bind hook that would manually bind the sysreset driver, if enabled, to the same RSTC DT node. Furthermore, delete the no longer needed compatibles from the SYSRESET driver and rename it to make sure than any possible conflicts are avoided. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> Tested-by: Mihai Sain <mihai.sain@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2023-01-04 16:03:18 +02:00
obj-$(CONFIG_RESET_AT91) += reset-at91.o
reset: starfive: jh7110: Add reset driver for StarFive JH7110 SoC Add a DM reset driver for StarFive JH7110 SoC. Note that the register base address of reset controller is the same with the clock controller. Therefore, there is no device tree node alone for reset driver.It binds device node in the clock driver Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com>
2023-03-29 11:42:11 +08:00
obj-$(CONFIG_$(SPL_TPL_)RESET_JH7110) += reset-jh7110.o
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