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u-boot/drivers/reset/Makefile

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Add a reset driver framework/uclass A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:43:58 +00:00
# Copyright (c) 2016, NVIDIA CORPORATION.
#
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DM_RESET) += reset-uclass.o
reset: implement a reset test This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:43:59 +00:00
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
reset: Add STi reset support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-22 09:54:03 +00:00
obj-$(CONFIG_STI_RESET) += sti-reset.o
dm: reset: add stm32 reset driver This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:07 +00:00
obj-$(CONFIG_STM32_RESET) += stm32-reset.o
reset: implement a driver for the Tegra CAR Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:58 +00:00
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
reset: add Tegra186 reset driver In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 17:28:25 +00:00
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
dm: reset: add BCM6345 reset driver This is a simplified version of linux/arch/mips/bcm63xx/reset.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-03 13:10:21 +00:00
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
reset: uniphier: add reset controller driver for UniPhier SoCs This is the initial commit for UniPhier reset controller driver. Most code was ported from Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-08 04:25:31 +00:00
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
aspeed: Reset Driver Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:24 +00:00
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
rockchip: reset: support a (common) rockchip reset drivers Create driver to support the soft reset (i.e. peripheral) of all Rockchip SoCs. Example of usage: i2c driver: ret = reset_get_by_name(dev, "i2c", &reset_ctl); if (ret) { error("reset_get_by_name() failed: %d\n", ret); } reset_assert(&reset_ctl); udelay(50); reset_deassert(&reset_ctl); i2c dts node: resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>; reset-names = "p_i2c", "i2c"; Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed commit tag:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-12-19 10:22:37 +00:00
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
reset: Add Amlogic Meson Reset Controller The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-29 12:55:25 +00:00
obj-$(CONFIG_RESET_MESON) += reset-meson.o
reset: socfpga: add reset driver for SoCFPGA platform Add a DM compatible reset driver for the SoCFPGA platform. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-04-04 22:18:20 +00:00
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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