2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2014-08-13 05:55:06 +00:00
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/*
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* Display driver for Allwinner SoCs.
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*
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* (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be>
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2015-08-03 17:20:26 +00:00
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* (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com>
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2014-08-13 05:55:06 +00:00
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*/
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#include <common.h>
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2021-02-22 00:12:34 +00:00
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#include <display.h>
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#include <dm.h>
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2019-11-14 19:57:39 +00:00
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#include <cpu_func.h>
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2018-03-03 09:30:17 +00:00
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#include <efi_loader.h>
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2019-11-14 19:57:45 +00:00
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#include <init.h>
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2019-11-14 19:57:30 +00:00
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#include <time.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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2014-08-13 05:55:06 +00:00
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#include <asm/arch/clock.h>
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#include <asm/arch/display.h>
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2017-03-27 17:22:29 +00:00
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#include <asm/arch/lcdc.h>
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2016-08-19 13:25:41 +00:00
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#include <asm/arch/pwm.h>
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2017-05-10 16:46:28 +00:00
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#include <asm/arch/tve.h>
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2014-08-13 05:55:06 +00:00
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#include <asm/global_data.h>
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2014-12-21 15:28:32 +00:00
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#include <asm/gpio.h>
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2014-08-13 05:55:06 +00:00
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#include <asm/io.h>
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2015-10-03 13:18:33 +00:00
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#include <axp_pmic.h>
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2014-12-19 15:05:12 +00:00
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#include <errno.h>
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2014-08-13 05:55:07 +00:00
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#include <fdtdec.h>
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#include <fdt_support.h>
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2015-02-16 16:49:47 +00:00
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#include <i2c.h>
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2015-08-04 22:06:47 +00:00
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#include <malloc.h>
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2021-02-22 00:12:34 +00:00
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#include <video.h>
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2014-08-13 05:55:06 +00:00
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#include <video_fb.h>
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2021-02-22 00:12:34 +00:00
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#include <dm/uclass-internal.h>
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2017-03-27 17:22:29 +00:00
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#include "../videomodes.h"
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#include "../anx9804.h"
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#include "../hitachi_tx18d42vm_lcd.h"
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#include "../ssd2828.h"
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2017-10-26 03:14:45 +00:00
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#include "simplefb_common.h"
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2014-08-13 05:55:06 +00:00
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2015-01-22 20:02:42 +00:00
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#ifdef CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW
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#define PWM_ON 0
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#define PWM_OFF 1
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#else
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#define PWM_ON 1
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#define PWM_OFF 0
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#endif
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2014-08-13 05:55:06 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2021-02-22 00:12:34 +00:00
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/* Maximum LCD size we support */
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#define LCD_MAX_WIDTH 3840
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#define LCD_MAX_HEIGHT 2160
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#define LCD_MAX_LOG2_BPP VIDEO_BPP32
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2014-12-21 13:37:45 +00:00
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enum sunxi_monitor {
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sunxi_monitor_none,
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sunxi_monitor_dvi,
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sunxi_monitor_hdmi,
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sunxi_monitor_lcd,
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sunxi_monitor_vga,
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2015-08-03 17:20:26 +00:00
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sunxi_monitor_composite_pal,
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sunxi_monitor_composite_ntsc,
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sunxi_monitor_composite_pal_m,
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sunxi_monitor_composite_pal_nc,
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2014-12-21 13:37:45 +00:00
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};
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2015-08-03 17:20:26 +00:00
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#define SUNXI_MONITOR_LAST sunxi_monitor_composite_pal_nc
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2014-12-21 13:37:45 +00:00
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2021-02-22 00:12:34 +00:00
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struct sunxi_display_priv {
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2014-12-21 13:37:45 +00:00
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enum sunxi_monitor monitor;
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2014-12-21 15:28:32 +00:00
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unsigned int depth;
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2015-08-04 22:06:47 +00:00
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unsigned int fb_addr;
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2015-02-02 17:00:53 +00:00
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unsigned int fb_size;
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2021-02-22 00:12:34 +00:00
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};
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2014-08-13 05:55:06 +00:00
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2015-08-03 17:20:26 +00:00
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const struct ctfb_res_modes composite_video_modes[2] = {
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/* x y hz pixclk ps/kHz le ri up lo hs vs s vmode */
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{ 720, 576, 50, 37037, 27000, 137, 5, 20, 27, 2, 2, 0, FB_VMODE_INTERLACED },
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{ 720, 480, 60, 37037, 27000, 116, 20, 16, 27, 2, 2, 0, FB_VMODE_INTERLACED },
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};
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2014-12-23 22:04:35 +00:00
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#ifdef CONFIG_VIDEO_HDMI
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2014-12-19 15:05:12 +00:00
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/*
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* Wait up to 200ms for value to be set in given part of reg.
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*/
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static int await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 200000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo) {
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printf("DDC: timeout reading EDID\n");
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return -ETIME;
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}
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}
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return 0;
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}
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2014-12-28 08:13:21 +00:00
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static int sunxi_hdmi_hpd_detect(int hpd_delay)
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2014-08-13 05:55:06 +00:00
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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2014-12-28 08:13:21 +00:00
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unsigned long tmo = timer_get_us() + hpd_delay * 1000;
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2014-08-13 05:55:06 +00:00
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/* Set pll3 to 300MHz */
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clock_set_pll3(300000000);
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/* Set hdmi parent to pll3 */
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clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
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CCM_HDMI_CTRL_PLL3);
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/* Set ahb gating to pass */
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2015-04-06 18:33:34 +00:00
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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2014-11-14 16:42:14 +00:00
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
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#endif
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2014-08-13 05:55:06 +00:00
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setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
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/* Clock on */
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setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
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writel(SUNXI_HDMI_CTRL_ENABLE, &hdmi->ctrl);
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writel(SUNXI_HDMI_PAD_CTRL0_HDP, &hdmi->pad_ctrl0);
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2018-12-19 13:06:08 +00:00
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/* Enable PLLs for eventual DDC */
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writel(SUNXI_HDMI_PAD_CTRL1 | SUNXI_HDMI_PAD_CTRL1_HALVE,
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&hdmi->pad_ctrl1);
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writel(SUNXI_HDMI_PLL_CTRL | SUNXI_HDMI_PLL_CTRL_DIV(15),
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&hdmi->pll_ctrl);
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writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
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2014-12-20 14:15:23 +00:00
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while (timer_get_us() < tmo) {
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if (readl(&hdmi->hpd) & SUNXI_HDMI_HPD_DETECT)
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return 1;
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}
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2014-08-13 05:55:06 +00:00
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2014-12-20 14:15:23 +00:00
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return 0;
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2014-12-19 14:13:57 +00:00
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}
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static void sunxi_hdmi_shutdown(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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2014-08-13 05:55:06 +00:00
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clrbits_le32(&hdmi->ctrl, SUNXI_HDMI_CTRL_ENABLE);
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clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
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clrbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
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2015-04-06 18:33:34 +00:00
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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2014-11-14 16:42:14 +00:00
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clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
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#endif
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2014-08-13 05:55:06 +00:00
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clock_set_pll3(0);
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}
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2014-12-19 15:05:12 +00:00
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static int sunxi_hdmi_ddc_do_command(u32 cmnd, int offset, int n)
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{
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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setbits_le32(&hdmi->ddc_fifo_ctrl, SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR);
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writel(SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(offset >> 8) |
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SUNXI_HMDI_DDC_ADDR_EDDC_ADDR |
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SUNXI_HMDI_DDC_ADDR_OFFSET(offset) |
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SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR, &hdmi->ddc_addr);
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#ifndef CONFIG_MACH_SUN6I
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writel(n, &hdmi->ddc_byte_count);
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writel(cmnd, &hdmi->ddc_cmnd);
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#else
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writel(n << 16 | cmnd, &hdmi->ddc_cmnd);
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#endif
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setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START);
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return await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START, 0);
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}
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static int sunxi_hdmi_ddc_read(int offset, u8 *buf, int count)
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{
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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int i, n;
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while (count > 0) {
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if (count > 16)
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n = 16;
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else
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n = count;
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if (sunxi_hdmi_ddc_do_command(
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SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ,
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offset, n))
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return -ETIME;
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for (i = 0; i < n; i++)
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*buf++ = readb(&hdmi->ddc_fifo_data);
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offset += n;
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count -= n;
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}
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return 0;
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}
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2014-12-20 13:01:48 +00:00
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static int sunxi_hdmi_edid_get_block(int block, u8 *buf)
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{
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int r, retries = 2;
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do {
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r = sunxi_hdmi_ddc_read(block * 128, buf, 128);
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if (r)
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continue;
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r = edid_check_checksum(buf);
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if (r) {
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printf("EDID block %d: checksum error%s\n",
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block, retries ? ", retrying" : "");
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}
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} while (r && retries--);
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return r;
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}
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2021-02-22 00:12:34 +00:00
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static int sunxi_hdmi_edid_get_mode(struct sunxi_display_priv *sunxi_display,
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struct ctfb_res_modes *mode,
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2018-12-19 13:06:09 +00:00
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bool verbose_mode)
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2014-12-19 15:05:12 +00:00
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{
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struct edid1_info edid1;
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2014-12-20 13:31:45 +00:00
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struct edid_cea861_info cea681[4];
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2014-12-19 15:05:12 +00:00
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struct edid_detailed_timing *t =
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(struct edid_detailed_timing *)edid1.monitor_details.timing;
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struct sunxi_hdmi_reg * const hdmi =
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(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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2014-12-20 13:31:45 +00:00
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int i, r, ext_blocks = 0;
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2014-12-19 15:05:12 +00:00
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/* Reset i2c controller */
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setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
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writel(SUNXI_HMDI_DDC_CTRL_ENABLE |
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SUNXI_HMDI_DDC_CTRL_SDA_ENABLE |
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SUNXI_HMDI_DDC_CTRL_SCL_ENABLE |
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SUNXI_HMDI_DDC_CTRL_RESET, &hdmi->ddc_ctrl);
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if (await_completion(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_RESET, 0))
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return -EIO;
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writel(SUNXI_HDMI_DDC_CLOCK, &hdmi->ddc_clock);
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#ifndef CONFIG_MACH_SUN6I
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writel(SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE |
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SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE, &hdmi->ddc_line_ctrl);
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#endif
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2014-12-20 13:01:48 +00:00
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r = sunxi_hdmi_edid_get_block(0, (u8 *)&edid1);
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2014-12-20 13:31:45 +00:00
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if (r == 0) {
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r = edid_check_info(&edid1);
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if (r) {
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2018-12-19 13:06:09 +00:00
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if (verbose_mode)
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printf("EDID: invalid EDID data\n");
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2014-12-20 13:31:45 +00:00
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r = -EINVAL;
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}
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}
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if (r == 0) {
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ext_blocks = edid1.extension_flag;
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if (ext_blocks > 4)
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ext_blocks = 4;
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for (i = 0; i < ext_blocks; i++) {
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if (sunxi_hdmi_edid_get_block(1 + i,
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(u8 *)&cea681[i]) != 0) {
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ext_blocks = i;
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break;
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}
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}
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}
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2014-12-19 15:05:12 +00:00
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/* Disable DDC engine, no longer needed */
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clrbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_ENABLE);
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clrbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE);
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if (r)
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return r;
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/* We want version 1.3 or 1.2 with detailed timing info */
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if (edid1.version != 1 || (edid1.revision < 3 &&
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!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(edid1))) {
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printf("EDID: unsupported version %d.%d\n",
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edid1.version, edid1.revision);
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return -EINVAL;
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}
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/* Take the first usable detailed timing */
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for (i = 0; i < 4; i++, t++) {
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r = video_edid_dtd_to_ctfb_res_modes(t, mode);
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|
|
if (r == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (i == 4) {
|
|
|
|
printf("EDID: no usable detailed timing found\n");
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
2014-12-20 13:31:45 +00:00
|
|
|
/* Check for basic audio support, if found enable hdmi output */
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_monitor_dvi;
|
2014-12-20 13:31:45 +00:00
|
|
|
for (i = 0; i < ext_blocks; i++) {
|
|
|
|
if (cea681[i].extension_tag != EDID_CEA861_EXTENSION_TAG ||
|
|
|
|
cea681[i].revision < 2)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (EDID_CEA861_SUPPORTS_BASIC_AUDIO(cea681[i]))
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_monitor_hdmi;
|
2014-12-20 13:31:45 +00:00
|
|
|
}
|
|
|
|
|
2014-12-19 15:05:12 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-12-23 22:04:35 +00:00
|
|
|
#endif /* CONFIG_VIDEO_HDMI */
|
|
|
|
|
2015-01-19 07:44:07 +00:00
|
|
|
#ifdef CONFIG_MACH_SUN4I
|
|
|
|
/*
|
|
|
|
* Testing has shown that on sun4i the display backend engine does not have
|
|
|
|
* deep enough fifo-s causing flickering / tearing in full-hd mode due to
|
|
|
|
* fifo underruns. So on sun4i we use the display frontend engine to do the
|
|
|
|
* dma from memory, as the frontend does have deep enough fifo-s.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static const u32 sun4i_vert_coef[32] = {
|
|
|
|
0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
|
|
|
|
0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
|
|
|
|
0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
|
|
|
|
0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
|
|
|
|
0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
|
|
|
|
0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
|
|
|
|
0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
|
|
|
|
0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const u32 sun4i_horz_coef[64] = {
|
|
|
|
0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
|
|
|
|
0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
|
|
|
|
0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
|
|
|
|
0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
|
|
|
|
0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
|
|
|
|
0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
|
|
|
|
0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
|
|
|
|
0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
|
|
|
|
0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
|
|
|
|
0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
|
|
|
|
0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
|
|
|
|
0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
|
|
|
|
0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
|
|
|
|
0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
|
|
|
|
0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
|
|
|
|
0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void sunxi_frontend_init(void)
|
|
|
|
{
|
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
struct sunxi_de_fe_reg * const de_fe =
|
|
|
|
(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Clocks on */
|
|
|
|
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_FE0);
|
|
|
|
setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_FE0);
|
|
|
|
clock_set_de_mod_clock(&ccm->fe0_clk_cfg, 300000000);
|
|
|
|
|
|
|
|
setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN);
|
|
|
|
|
|
|
|
for (i = 0; i < 32; i++) {
|
|
|
|
writel(sun4i_horz_coef[2 * i], &de_fe->ch0_horzcoef0[i]);
|
|
|
|
writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch0_horzcoef1[i]);
|
|
|
|
writel(sun4i_vert_coef[i], &de_fe->ch0_vertcoef[i]);
|
|
|
|
writel(sun4i_horz_coef[2 * i], &de_fe->ch1_horzcoef0[i]);
|
|
|
|
writel(sun4i_horz_coef[2 * i + 1], &de_fe->ch1_horzcoef1[i]);
|
|
|
|
writel(sun4i_vert_coef[i], &de_fe->ch1_vertcoef[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_COEF_RDY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
|
|
|
|
unsigned int address)
|
|
|
|
{
|
|
|
|
struct sunxi_de_fe_reg * const de_fe =
|
|
|
|
(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
|
|
|
|
|
|
|
|
setbits_le32(&de_fe->bypass, SUNXI_DE_FE_BYPASS_CSC_BYPASS);
|
|
|
|
writel(CONFIG_SYS_SDRAM_BASE + address, &de_fe->ch0_addr);
|
|
|
|
writel(mode->xres * 4, &de_fe->ch0_stride);
|
|
|
|
writel(SUNXI_DE_FE_INPUT_FMT_ARGB8888, &de_fe->input_fmt);
|
|
|
|
writel(SUNXI_DE_FE_OUTPUT_FMT_ARGB8888, &de_fe->output_fmt);
|
|
|
|
|
|
|
|
writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
|
|
|
|
&de_fe->ch0_insize);
|
|
|
|
writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
|
|
|
|
&de_fe->ch0_outsize);
|
|
|
|
writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_horzfact);
|
|
|
|
writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch0_vertfact);
|
|
|
|
|
|
|
|
writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
|
|
|
|
&de_fe->ch1_insize);
|
|
|
|
writel(SUNXI_DE_FE_HEIGHT(mode->yres) | SUNXI_DE_FE_WIDTH(mode->xres),
|
|
|
|
&de_fe->ch1_outsize);
|
|
|
|
writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_horzfact);
|
|
|
|
writel(SUNXI_DE_FE_FACTOR_INT(1), &de_fe->ch1_vertfact);
|
|
|
|
|
|
|
|
setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_REG_RDY);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sunxi_frontend_enable(void)
|
|
|
|
{
|
|
|
|
struct sunxi_de_fe_reg * const de_fe =
|
|
|
|
(struct sunxi_de_fe_reg *)SUNXI_DE_FE0_BASE;
|
|
|
|
|
|
|
|
setbits_le32(&de_fe->frame_ctrl, SUNXI_DE_FE_FRAME_CTRL_FRM_START);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
static void sunxi_frontend_init(void) {}
|
|
|
|
static void sunxi_frontend_mode_set(const struct ctfb_res_modes *mode,
|
|
|
|
unsigned int address) {}
|
|
|
|
static void sunxi_frontend_enable(void) {}
|
|
|
|
#endif
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
static bool sunxi_is_composite(enum sunxi_monitor monitor)
|
2015-08-03 17:20:26 +00:00
|
|
|
{
|
2021-02-22 00:12:34 +00:00
|
|
|
switch (monitor) {
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_none:
|
|
|
|
case sunxi_monitor_dvi:
|
|
|
|
case sunxi_monitor_hdmi:
|
|
|
|
case sunxi_monitor_lcd:
|
|
|
|
case sunxi_monitor_vga:
|
|
|
|
return false;
|
|
|
|
case sunxi_monitor_composite_pal:
|
|
|
|
case sunxi_monitor_composite_ntsc:
|
|
|
|
case sunxi_monitor_composite_pal_m:
|
|
|
|
case sunxi_monitor_composite_pal_nc:
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false; /* Never reached */
|
|
|
|
}
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
/*
|
|
|
|
* This is the entity that mixes and matches the different layers and inputs.
|
|
|
|
* Allwinner calls it the back-end, but i like composer better.
|
|
|
|
*/
|
|
|
|
static void sunxi_composer_init(void)
|
|
|
|
{
|
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
struct sunxi_de_be_reg * const de_be =
|
|
|
|
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
|
|
|
|
int i;
|
|
|
|
|
2015-01-19 07:44:07 +00:00
|
|
|
sunxi_frontend_init();
|
|
|
|
|
2015-04-06 18:33:34 +00:00
|
|
|
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
2014-11-14 16:42:14 +00:00
|
|
|
/* Reset off */
|
|
|
|
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0);
|
|
|
|
#endif
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
/* Clocks on */
|
|
|
|
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE_BE0);
|
2015-01-19 07:44:07 +00:00
|
|
|
#ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
|
2014-08-13 05:55:06 +00:00
|
|
|
setbits_le32(&ccm->dram_clk_gate, 1 << CCM_DRAM_GATE_OFFSET_DE_BE0);
|
2015-01-19 07:44:07 +00:00
|
|
|
#endif
|
2014-08-13 05:55:06 +00:00
|
|
|
clock_set_de_mod_clock(&ccm->be0_clk_cfg, 300000000);
|
|
|
|
|
|
|
|
/* Engine bug, clear registers after reset */
|
|
|
|
for (i = 0x0800; i < 0x1000; i += 4)
|
|
|
|
writel(0, SUNXI_DE_BE0_BASE + i);
|
|
|
|
|
|
|
|
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE);
|
|
|
|
}
|
|
|
|
|
2018-10-23 17:20:31 +00:00
|
|
|
static const u32 sunxi_rgb2yuv_coef[12] = {
|
2015-08-03 17:20:26 +00:00
|
|
|
0x00000107, 0x00000204, 0x00000064, 0x00000108,
|
|
|
|
0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
|
|
|
|
0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
|
|
|
|
};
|
|
|
|
|
2014-12-19 12:46:33 +00:00
|
|
|
static void sunxi_composer_mode_set(const struct ctfb_res_modes *mode,
|
2021-02-22 00:12:34 +00:00
|
|
|
unsigned int address,
|
|
|
|
enum sunxi_monitor monitor)
|
2014-08-13 05:55:06 +00:00
|
|
|
{
|
|
|
|
struct sunxi_de_be_reg * const de_be =
|
|
|
|
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
|
2015-08-03 17:20:26 +00:00
|
|
|
int i;
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2015-01-19 07:44:07 +00:00
|
|
|
sunxi_frontend_mode_set(mode, address);
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
|
|
|
|
&de_be->disp_size);
|
|
|
|
writel(SUNXI_DE_BE_HEIGHT(mode->yres) | SUNXI_DE_BE_WIDTH(mode->xres),
|
|
|
|
&de_be->layer0_size);
|
2015-01-19 07:44:07 +00:00
|
|
|
#ifndef CONFIG_MACH_SUN4I /* On sun4i the frontend does the dma */
|
2014-08-13 05:55:06 +00:00
|
|
|
writel(SUNXI_DE_BE_LAYER_STRIDE(mode->xres), &de_be->layer0_stride);
|
|
|
|
writel(address << 3, &de_be->layer0_addr_low32b);
|
|
|
|
writel(address >> 29, &de_be->layer0_addr_high4b);
|
2015-01-19 07:44:07 +00:00
|
|
|
#else
|
|
|
|
writel(SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0, &de_be->layer0_attr0_ctrl);
|
|
|
|
#endif
|
2014-08-13 05:55:06 +00:00
|
|
|
writel(SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888, &de_be->layer0_attr1_ctrl);
|
|
|
|
|
|
|
|
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_LAYER0_ENABLE);
|
2015-08-02 14:49:29 +00:00
|
|
|
if (mode->vmode == FB_VMODE_INTERLACED)
|
|
|
|
setbits_le32(&de_be->mode,
|
2015-08-06 10:08:33 +00:00
|
|
|
#ifndef CONFIG_MACH_SUN5I
|
2015-08-02 14:49:29 +00:00
|
|
|
SUNXI_DE_BE_MODE_DEFLICKER_ENABLE |
|
2015-08-06 10:08:33 +00:00
|
|
|
#endif
|
2015-08-02 14:49:29 +00:00
|
|
|
SUNXI_DE_BE_MODE_INTERLACE_ENABLE);
|
2015-08-03 17:20:26 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
if (sunxi_is_composite(monitor)) {
|
2015-08-03 17:20:26 +00:00
|
|
|
writel(SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE,
|
|
|
|
&de_be->output_color_ctrl);
|
|
|
|
for (i = 0; i < 12; i++)
|
|
|
|
writel(sunxi_rgb2yuv_coef[i],
|
|
|
|
&de_be->output_color_coef[i]);
|
|
|
|
}
|
2014-08-13 05:55:06 +00:00
|
|
|
}
|
|
|
|
|
2014-12-21 13:49:34 +00:00
|
|
|
static void sunxi_composer_enable(void)
|
|
|
|
{
|
|
|
|
struct sunxi_de_be_reg * const de_be =
|
|
|
|
(struct sunxi_de_be_reg *)SUNXI_DE_BE0_BASE;
|
|
|
|
|
2015-01-19 07:44:07 +00:00
|
|
|
sunxi_frontend_enable();
|
|
|
|
|
2014-12-21 13:49:34 +00:00
|
|
|
setbits_le32(&de_be->reg_ctrl, SUNXI_DE_BE_REG_CTRL_LOAD_REGS);
|
|
|
|
setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START);
|
|
|
|
}
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
static void sunxi_lcdc_init(void)
|
|
|
|
{
|
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
struct sunxi_lcdc_reg * const lcdc =
|
|
|
|
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
|
|
|
|
|
|
|
/* Reset off */
|
2015-04-06 18:33:34 +00:00
|
|
|
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
2014-11-14 16:42:14 +00:00
|
|
|
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
|
|
|
|
#else
|
2014-08-13 05:55:06 +00:00
|
|
|
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST);
|
2014-11-14 16:42:14 +00:00
|
|
|
#endif
|
2014-08-13 05:55:06 +00:00
|
|
|
|
|
|
|
/* Clock on */
|
|
|
|
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
|
2015-01-01 21:04:34 +00:00
|
|
|
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
|
2015-05-14 16:52:54 +00:00
|
|
|
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
|
|
|
setbits_le32(&ccm->ahb_reset2_cfg, 1 << AHB_RESET_OFFSET_LVDS);
|
|
|
|
#else
|
2015-01-01 21:04:34 +00:00
|
|
|
setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST);
|
2015-05-14 16:52:54 +00:00
|
|
|
#endif
|
2015-01-01 21:04:34 +00:00
|
|
|
#endif
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2017-03-27 17:22:29 +00:00
|
|
|
lcdc_init(lcdc);
|
2014-12-21 13:49:34 +00:00
|
|
|
}
|
|
|
|
|
2014-12-21 15:28:32 +00:00
|
|
|
static void sunxi_lcdc_panel_enable(void)
|
|
|
|
{
|
2015-02-16 16:26:41 +00:00
|
|
|
int pin, reset_pin;
|
2014-12-21 15:28:32 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Start with backlight disabled to avoid the screen flashing to
|
|
|
|
* white while the lcd inits.
|
|
|
|
*/
|
|
|
|
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
|
2015-04-22 15:45:59 +00:00
|
|
|
if (pin >= 0) {
|
2014-12-21 15:28:32 +00:00
|
|
|
gpio_request(pin, "lcd_backlight_enable");
|
|
|
|
gpio_direction_output(pin, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
|
2015-04-22 15:45:59 +00:00
|
|
|
if (pin >= 0) {
|
2014-12-21 15:28:32 +00:00
|
|
|
gpio_request(pin, "lcd_backlight_pwm");
|
2015-01-22 20:02:42 +00:00
|
|
|
gpio_direction_output(pin, PWM_OFF);
|
2014-12-21 15:28:32 +00:00
|
|
|
}
|
|
|
|
|
2015-02-16 16:26:41 +00:00
|
|
|
reset_pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_RESET);
|
2015-04-22 15:45:59 +00:00
|
|
|
if (reset_pin >= 0) {
|
2015-02-16 16:26:41 +00:00
|
|
|
gpio_request(reset_pin, "lcd_reset");
|
|
|
|
gpio_direction_output(reset_pin, 0); /* Assert reset */
|
|
|
|
}
|
|
|
|
|
2014-12-21 15:28:32 +00:00
|
|
|
/* Give the backlight some time to turn off and power up the panel. */
|
|
|
|
mdelay(40);
|
|
|
|
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_POWER);
|
2015-04-22 15:45:59 +00:00
|
|
|
if (pin >= 0) {
|
2014-12-21 15:28:32 +00:00
|
|
|
gpio_request(pin, "lcd_power");
|
|
|
|
gpio_direction_output(pin, 1);
|
|
|
|
}
|
2015-02-16 16:26:41 +00:00
|
|
|
|
2015-04-22 15:45:59 +00:00
|
|
|
if (reset_pin >= 0)
|
2015-02-16 16:26:41 +00:00
|
|
|
gpio_direction_output(reset_pin, 1); /* De-assert reset */
|
2014-12-21 15:28:32 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sunxi_lcdc_backlight_enable(void)
|
|
|
|
{
|
|
|
|
int pin;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We want to have scanned out at least one frame before enabling the
|
|
|
|
* backlight to avoid the screen flashing to white when we enable it.
|
|
|
|
*/
|
|
|
|
mdelay(40);
|
|
|
|
|
|
|
|
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_EN);
|
2015-04-22 15:45:59 +00:00
|
|
|
if (pin >= 0)
|
2014-12-21 15:28:32 +00:00
|
|
|
gpio_direction_output(pin, 1);
|
|
|
|
|
|
|
|
pin = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_BL_PWM);
|
2016-08-19 13:25:41 +00:00
|
|
|
#ifdef SUNXI_PWM_PIN0
|
|
|
|
if (pin == SUNXI_PWM_PIN0) {
|
|
|
|
writel(SUNXI_PWM_CTRL_POLARITY0(PWM_ON) |
|
|
|
|
SUNXI_PWM_CTRL_ENABLE0 |
|
|
|
|
SUNXI_PWM_CTRL_PRESCALE0(0xf), SUNXI_PWM_CTRL_REG);
|
|
|
|
writel(SUNXI_PWM_PERIOD_80PCT, SUNXI_PWM_CH0_PERIOD);
|
|
|
|
sunxi_gpio_set_cfgpin(pin, SUNXI_PWM_MUX);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
2015-04-22 15:45:59 +00:00
|
|
|
if (pin >= 0)
|
2015-01-22 20:02:42 +00:00
|
|
|
gpio_direction_output(pin, PWM_ON);
|
2014-12-21 15:28:32 +00:00
|
|
|
}
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
static void sunxi_lcdc_tcon0_mode_set(struct sunxi_display_priv *sunxi_display,
|
|
|
|
const struct ctfb_res_modes *mode,
|
2015-01-25 14:33:07 +00:00
|
|
|
bool for_ext_vga_dac)
|
2014-12-21 15:28:32 +00:00
|
|
|
{
|
|
|
|
struct sunxi_lcdc_reg * const lcdc =
|
|
|
|
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
2017-10-27 04:51:51 +00:00
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
2017-03-27 17:22:29 +00:00
|
|
|
int clk_div, clk_double, pin;
|
2017-03-27 17:22:30 +00:00
|
|
|
struct display_timing timing;
|
2014-12-21 15:28:32 +00:00
|
|
|
|
2016-03-04 17:08:56 +00:00
|
|
|
#if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
|
|
|
|
for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {
|
|
|
|
#else
|
2015-08-08 14:13:53 +00:00
|
|
|
for (pin = SUNXI_GPD(0); pin <= SUNXI_GPD(27); pin++) {
|
2016-03-04 17:08:56 +00:00
|
|
|
#endif
|
2015-01-01 21:04:34 +00:00
|
|
|
#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
|
2015-03-22 17:12:22 +00:00
|
|
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
|
2015-01-01 21:04:34 +00:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_VIDEO_LCD_IF_LVDS
|
2015-03-22 17:12:22 +00:00
|
|
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LVDS0);
|
2015-01-01 21:04:34 +00:00
|
|
|
#endif
|
2015-08-08 14:13:53 +00:00
|
|
|
#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
|
|
|
|
sunxi_gpio_set_drv(pin, 3);
|
|
|
|
#endif
|
|
|
|
}
|
2014-12-21 15:28:32 +00:00
|
|
|
|
2017-10-27 04:51:51 +00:00
|
|
|
lcdc_pll_set(ccm, 0, mode->pixclock_khz, &clk_div, &clk_double,
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_is_composite(sunxi_display->monitor));
|
2014-12-21 15:28:32 +00:00
|
|
|
|
2020-04-08 15:10:12 +00:00
|
|
|
video_ctfb_mode_to_display_timing(mode, &timing);
|
2017-03-27 17:22:30 +00:00
|
|
|
lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
|
2014-12-21 15:28:32 +00:00
|
|
|
}
|
|
|
|
|
2015-08-03 17:20:26 +00:00
|
|
|
#if defined CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
|
2014-12-21 13:49:34 +00:00
|
|
|
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
|
2014-12-27 14:19:23 +00:00
|
|
|
int *clk_div, int *clk_double,
|
2021-02-22 00:12:34 +00:00
|
|
|
bool use_portd_hvsync,
|
|
|
|
enum sunxi_monitor monitor)
|
2014-08-13 05:55:06 +00:00
|
|
|
{
|
|
|
|
struct sunxi_lcdc_reg * const lcdc =
|
|
|
|
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
2017-10-27 04:51:51 +00:00
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
2017-03-27 17:22:30 +00:00
|
|
|
struct display_timing timing;
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2020-04-08 15:10:12 +00:00
|
|
|
video_ctfb_mode_to_display_timing(mode, &timing);
|
2017-03-27 17:22:30 +00:00
|
|
|
lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_is_composite(monitor));
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2014-12-27 14:19:23 +00:00
|
|
|
if (use_portd_hvsync) {
|
2015-03-22 17:12:22 +00:00
|
|
|
sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0);
|
|
|
|
sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0);
|
2014-12-27 14:19:23 +00:00
|
|
|
}
|
2015-08-06 10:08:33 +00:00
|
|
|
|
2017-10-27 04:51:51 +00:00
|
|
|
lcdc_pll_set(ccm, 1, mode->pixclock_khz, clk_div, clk_double,
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_is_composite(monitor));
|
2014-08-13 05:55:06 +00:00
|
|
|
}
|
2015-08-03 17:20:26 +00:00
|
|
|
#endif /* CONFIG_VIDEO_HDMI || defined CONFIG_VIDEO_VGA || CONFIG_VIDEO_COMPOSITE */
|
2014-12-25 12:58:06 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_VIDEO_HDMI
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2014-12-20 12:38:06 +00:00
|
|
|
static void sunxi_hdmi_setup_info_frames(const struct ctfb_res_modes *mode)
|
|
|
|
{
|
|
|
|
struct sunxi_hdmi_reg * const hdmi =
|
|
|
|
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
|
|
|
|
u8 checksum = 0;
|
|
|
|
u8 avi_info_frame[17] = {
|
|
|
|
0x82, 0x02, 0x0d, 0x00, 0x12, 0x00, 0x88, 0x00,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
0x00
|
|
|
|
};
|
|
|
|
u8 vendor_info_frame[19] = {
|
|
|
|
0x81, 0x01, 0x06, 0x29, 0x03, 0x0c, 0x00, 0x40,
|
|
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
|
|
0x00, 0x00, 0x00
|
|
|
|
};
|
|
|
|
int i;
|
|
|
|
|
|
|
|
if (mode->pixclock_khz <= 27000)
|
|
|
|
avi_info_frame[5] = 0x40; /* SD-modes, ITU601 colorspace */
|
|
|
|
else
|
|
|
|
avi_info_frame[5] = 0x80; /* HD-modes, ITU709 colorspace */
|
|
|
|
|
|
|
|
if (mode->xres * 100 / mode->yres < 156)
|
|
|
|
avi_info_frame[5] |= 0x18; /* 4 : 3 */
|
|
|
|
else
|
|
|
|
avi_info_frame[5] |= 0x28; /* 16 : 9 */
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
|
|
|
|
checksum += avi_info_frame[i];
|
|
|
|
|
|
|
|
avi_info_frame[3] = 0x100 - checksum;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(avi_info_frame); i++)
|
|
|
|
writeb(avi_info_frame[i], &hdmi->avi_info_frame[i]);
|
|
|
|
|
|
|
|
writel(SUNXI_HDMI_QCP_PACKET0, &hdmi->qcp_packet0);
|
|
|
|
writel(SUNXI_HDMI_QCP_PACKET1, &hdmi->qcp_packet1);
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(vendor_info_frame); i++)
|
|
|
|
writeb(vendor_info_frame[i], &hdmi->vendor_info_frame[i]);
|
|
|
|
|
|
|
|
writel(SUNXI_HDMI_PKT_CTRL0, &hdmi->pkt_ctrl0);
|
|
|
|
writel(SUNXI_HDMI_PKT_CTRL1, &hdmi->pkt_ctrl1);
|
|
|
|
|
|
|
|
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_HDMI);
|
|
|
|
}
|
|
|
|
|
2014-12-19 12:46:33 +00:00
|
|
|
static void sunxi_hdmi_mode_set(const struct ctfb_res_modes *mode,
|
2021-02-22 00:12:34 +00:00
|
|
|
int clk_div, int clk_double,
|
|
|
|
enum sunxi_monitor monitor)
|
2014-08-13 05:55:06 +00:00
|
|
|
{
|
|
|
|
struct sunxi_hdmi_reg * const hdmi =
|
|
|
|
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
|
|
|
|
int x, y;
|
|
|
|
|
|
|
|
/* Write clear interrupt status bits */
|
|
|
|
writel(SUNXI_HDMI_IRQ_STATUS_BITS, &hdmi->irq);
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
if (monitor == sunxi_monitor_hdmi)
|
2014-12-20 12:38:06 +00:00
|
|
|
sunxi_hdmi_setup_info_frames(mode);
|
|
|
|
|
2014-12-20 12:51:16 +00:00
|
|
|
/* Set input sync enable */
|
|
|
|
writel(SUNXI_HDMI_UNKNOWN_INPUT_SYNC, &hdmi->unknown);
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
/* Init various registers, select pll3 as clock source */
|
|
|
|
writel(SUNXI_HDMI_VIDEO_POL_TX_CLK, &hdmi->video_polarity);
|
|
|
|
writel(SUNXI_HDMI_PAD_CTRL0_RUN, &hdmi->pad_ctrl0);
|
|
|
|
writel(SUNXI_HDMI_PAD_CTRL1, &hdmi->pad_ctrl1);
|
|
|
|
writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
|
|
|
|
writel(SUNXI_HDMI_PLL_DBG0_PLL3, &hdmi->pll_dbg0);
|
|
|
|
|
|
|
|
/* Setup clk div and doubler */
|
|
|
|
clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
|
|
|
|
SUNXI_HDMI_PLL_CTRL_DIV(clk_div));
|
|
|
|
if (!clk_double)
|
|
|
|
setbits_le32(&hdmi->pad_ctrl1, SUNXI_HDMI_PAD_CTRL1_HALVE);
|
|
|
|
|
|
|
|
/* Setup timing registers */
|
|
|
|
writel(SUNXI_HDMI_Y(mode->yres) | SUNXI_HDMI_X(mode->xres),
|
|
|
|
&hdmi->video_size);
|
|
|
|
|
|
|
|
x = mode->hsync_len + mode->left_margin;
|
|
|
|
y = mode->vsync_len + mode->upper_margin;
|
|
|
|
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_bp);
|
|
|
|
|
|
|
|
x = mode->right_margin;
|
|
|
|
y = mode->lower_margin;
|
|
|
|
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_fp);
|
|
|
|
|
|
|
|
x = mode->hsync_len;
|
|
|
|
y = mode->vsync_len;
|
|
|
|
writel(SUNXI_HDMI_Y(y) | SUNXI_HDMI_X(x), &hdmi->video_spw);
|
|
|
|
|
|
|
|
if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
|
|
|
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_HOR);
|
|
|
|
|
|
|
|
if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
|
|
|
setbits_le32(&hdmi->video_polarity, SUNXI_HDMI_VIDEO_POL_VER);
|
|
|
|
}
|
|
|
|
|
2014-12-21 13:49:34 +00:00
|
|
|
static void sunxi_hdmi_enable(void)
|
|
|
|
{
|
|
|
|
struct sunxi_hdmi_reg * const hdmi =
|
|
|
|
(struct sunxi_hdmi_reg *)SUNXI_HDMI_BASE;
|
|
|
|
|
|
|
|
udelay(100);
|
|
|
|
setbits_le32(&hdmi->video_ctrl, SUNXI_HDMI_VIDEO_CTRL_ENABLE);
|
|
|
|
}
|
|
|
|
|
2014-12-23 22:04:35 +00:00
|
|
|
#endif /* CONFIG_VIDEO_HDMI */
|
|
|
|
|
2015-08-03 17:20:26 +00:00
|
|
|
#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE
|
2014-12-25 12:58:06 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
static void sunxi_tvencoder_mode_set(enum sunxi_monitor monitor)
|
2014-12-25 12:58:06 +00:00
|
|
|
{
|
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
struct sunxi_tve_reg * const tve =
|
|
|
|
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
|
|
|
|
|
2015-08-06 10:08:33 +00:00
|
|
|
/* Reset off */
|
|
|
|
setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);
|
2014-12-25 12:58:06 +00:00
|
|
|
/* Clock on */
|
|
|
|
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_TVE0);
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
switch (monitor) {
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_vga:
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_mode_set(tve, tve_mode_vga);
|
2015-08-03 17:20:26 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_composite_pal_nc:
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_mode_set(tve, tve_mode_composite_pal_nc);
|
|
|
|
break;
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_composite_pal:
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_mode_set(tve, tve_mode_composite_pal);
|
2015-08-03 17:20:26 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_composite_pal_m:
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_mode_set(tve, tve_mode_composite_pal_m);
|
|
|
|
break;
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_composite_ntsc:
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_mode_set(tve, tve_mode_composite_ntsc);
|
2015-08-03 17:20:26 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_none:
|
|
|
|
case sunxi_monitor_dvi:
|
|
|
|
case sunxi_monitor_hdmi:
|
|
|
|
case sunxi_monitor_lcd:
|
|
|
|
break;
|
|
|
|
}
|
2014-12-25 12:58:06 +00:00
|
|
|
}
|
|
|
|
|
2015-08-03 17:20:26 +00:00
|
|
|
#endif /* CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_COMPOSITE */
|
2014-12-25 12:58:06 +00:00
|
|
|
|
2014-12-23 17:39:52 +00:00
|
|
|
static void sunxi_drc_init(void)
|
|
|
|
{
|
2015-04-06 18:33:34 +00:00
|
|
|
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
2014-12-23 17:39:52 +00:00
|
|
|
struct sunxi_ccm_reg * const ccm =
|
|
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
|
|
|
|
/* On sun6i the drc must be clocked even when in pass-through mode */
|
2015-03-01 18:17:48 +00:00
|
|
|
#ifdef CONFIG_MACH_SUN8I_A33
|
|
|
|
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
|
|
|
|
#endif
|
2014-12-23 17:39:52 +00:00
|
|
|
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
|
|
|
|
clock_set_de_mod_clock(&ccm->iep_drc0_clk_cfg, 300000000);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2015-01-12 10:02:11 +00:00
|
|
|
#ifdef CONFIG_VIDEO_VGA_VIA_LCD
|
|
|
|
static void sunxi_vga_external_dac_enable(void)
|
|
|
|
{
|
|
|
|
int pin;
|
|
|
|
|
|
|
|
pin = sunxi_name_to_gpio(CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN);
|
2015-04-22 15:45:59 +00:00
|
|
|
if (pin >= 0) {
|
2015-01-12 10:02:11 +00:00
|
|
|
gpio_request(pin, "vga_enable");
|
|
|
|
gpio_direction_output(pin, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_VIDEO_VGA_VIA_LCD */
|
|
|
|
|
2015-01-19 03:23:33 +00:00
|
|
|
#ifdef CONFIG_VIDEO_LCD_SSD2828
|
|
|
|
static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
|
|
|
|
{
|
|
|
|
struct ssd2828_config cfg = {
|
|
|
|
.csx_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS),
|
|
|
|
.sck_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_SCLK),
|
|
|
|
.sdi_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MOSI),
|
|
|
|
.sdo_pin = name_to_gpio(CONFIG_VIDEO_LCD_SPI_MISO),
|
|
|
|
.reset_pin = name_to_gpio(CONFIG_VIDEO_LCD_SSD2828_RESET),
|
|
|
|
.ssd2828_tx_clk_khz = CONFIG_VIDEO_LCD_SSD2828_TX_CLK * 1000,
|
|
|
|
.ssd2828_color_depth = 24,
|
|
|
|
#ifdef CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
|
|
|
|
.mipi_dsi_number_of_data_lanes = 4,
|
|
|
|
.mipi_dsi_bitrate_per_data_lane_mbps = 513,
|
|
|
|
.mipi_dsi_delay_after_exit_sleep_mode_ms = 100,
|
|
|
|
.mipi_dsi_delay_after_set_display_on_ms = 200
|
|
|
|
#else
|
|
|
|
#error MIPI LCD panel needs configuration parameters
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
|
|
|
if (cfg.csx_pin == -1 || cfg.sck_pin == -1 || cfg.sdi_pin == -1) {
|
|
|
|
printf("SSD2828: SPI pins are not properly configured\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
if (cfg.reset_pin == -1) {
|
|
|
|
printf("SSD2828: Reset pin is not properly configured\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ssd2828_init(&cfg, mode);
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_VIDEO_LCD_SSD2828 */
|
|
|
|
|
2014-08-13 05:55:06 +00:00
|
|
|
static void sunxi_engines_init(void)
|
|
|
|
{
|
|
|
|
sunxi_composer_init();
|
|
|
|
sunxi_lcdc_init();
|
2014-11-14 16:42:14 +00:00
|
|
|
sunxi_drc_init();
|
2014-08-13 05:55:06 +00:00
|
|
|
}
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
static void sunxi_mode_set(struct sunxi_display_priv *sunxi_display,
|
|
|
|
const struct ctfb_res_modes *mode,
|
2014-12-20 12:38:06 +00:00
|
|
|
unsigned int address)
|
2014-08-13 05:55:06 +00:00
|
|
|
{
|
2021-02-22 00:12:34 +00:00
|
|
|
enum sunxi_monitor monitor = sunxi_display->monitor;
|
2014-12-25 12:58:06 +00:00
|
|
|
int __maybe_unused clk_div, clk_double;
|
2017-03-27 17:22:29 +00:00
|
|
|
struct sunxi_lcdc_reg * const lcdc =
|
|
|
|
(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
2017-05-10 16:46:28 +00:00
|
|
|
struct sunxi_tve_reg * __maybe_unused const tve =
|
|
|
|
(struct sunxi_tve_reg *)SUNXI_TVE0_BASE;
|
2014-12-25 12:58:06 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
switch (sunxi_display->monitor) {
|
2014-12-21 13:49:34 +00:00
|
|
|
case sunxi_monitor_none:
|
|
|
|
break;
|
|
|
|
case sunxi_monitor_dvi:
|
2014-12-25 12:58:06 +00:00
|
|
|
case sunxi_monitor_hdmi:
|
2014-12-23 22:04:35 +00:00
|
|
|
#ifdef CONFIG_VIDEO_HDMI
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_composer_mode_set(mode, address, monitor);
|
|
|
|
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0, monitor);
|
|
|
|
sunxi_hdmi_mode_set(mode, clk_div, clk_double, monitor);
|
2014-12-21 13:49:34 +00:00
|
|
|
sunxi_composer_enable();
|
2021-02-22 00:12:34 +00:00
|
|
|
lcdc_enable(lcdc, sunxi_display->depth);
|
2014-12-21 13:49:34 +00:00
|
|
|
sunxi_hdmi_enable();
|
2014-12-23 22:04:35 +00:00
|
|
|
#endif
|
2014-12-21 13:49:34 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_lcd:
|
2014-12-21 15:28:32 +00:00
|
|
|
sunxi_lcdc_panel_enable();
|
2015-08-08 14:13:53 +00:00
|
|
|
if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
|
|
|
|
/*
|
|
|
|
* The anx9804 needs 1.8V from eldo3, we do this here
|
2015-10-03 13:18:33 +00:00
|
|
|
* and not via CONFIG_AXP_ELDO3_VOLT from board_init()
|
2015-08-08 14:13:53 +00:00
|
|
|
* to avoid turning this on when using hdmi output.
|
|
|
|
*/
|
2015-10-03 13:18:33 +00:00
|
|
|
axp_set_eldo(3, 1800);
|
2015-08-08 14:13:53 +00:00
|
|
|
anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
|
|
|
|
ANX9804_DATA_RATE_1620M,
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->depth);
|
2015-08-08 14:13:53 +00:00
|
|
|
}
|
2015-01-20 08:23:36 +00:00
|
|
|
if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
|
|
|
|
mdelay(50); /* Wait for lcd controller power on */
|
|
|
|
hitachi_tx18d42vm_init();
|
|
|
|
}
|
2015-02-16 16:49:47 +00:00
|
|
|
if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
|
|
|
|
unsigned int orig_i2c_bus = i2c_get_bus_num();
|
|
|
|
i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
|
|
|
|
i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
|
|
|
|
i2c_set_bus_num(orig_i2c_bus);
|
|
|
|
}
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_composer_mode_set(mode, address, monitor);
|
|
|
|
sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false);
|
2014-12-21 15:28:32 +00:00
|
|
|
sunxi_composer_enable();
|
2021-02-22 00:12:34 +00:00
|
|
|
lcdc_enable(lcdc, sunxi_display->depth);
|
2015-01-19 03:23:33 +00:00
|
|
|
#ifdef CONFIG_VIDEO_LCD_SSD2828
|
|
|
|
sunxi_ssd2828_init(mode);
|
|
|
|
#endif
|
2014-12-21 15:28:32 +00:00
|
|
|
sunxi_lcdc_backlight_enable();
|
2014-12-21 13:49:34 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_vga:
|
2014-12-25 12:58:06 +00:00
|
|
|
#ifdef CONFIG_VIDEO_VGA
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_composer_mode_set(mode, address, monitor);
|
|
|
|
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 1, monitor);
|
|
|
|
sunxi_tvencoder_mode_set(monitor);
|
2014-12-25 12:58:06 +00:00
|
|
|
sunxi_composer_enable();
|
2021-02-22 00:12:34 +00:00
|
|
|
lcdc_enable(lcdc, sunxi_display->depth);
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_enable(tve);
|
2014-12-25 12:58:06 +00:00
|
|
|
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_composer_mode_set(mode, address, monitor);
|
|
|
|
sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, true);
|
2014-12-24 11:17:07 +00:00
|
|
|
sunxi_composer_enable();
|
2021-02-22 00:12:34 +00:00
|
|
|
lcdc_enable(lcdc, sunxi_display->depth);
|
2015-01-12 10:02:11 +00:00
|
|
|
sunxi_vga_external_dac_enable();
|
2015-08-03 17:20:26 +00:00
|
|
|
#endif
|
|
|
|
break;
|
|
|
|
case sunxi_monitor_composite_pal:
|
|
|
|
case sunxi_monitor_composite_ntsc:
|
|
|
|
case sunxi_monitor_composite_pal_m:
|
|
|
|
case sunxi_monitor_composite_pal_nc:
|
|
|
|
#ifdef CONFIG_VIDEO_COMPOSITE
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_composer_mode_set(mode, address, monitor);
|
|
|
|
sunxi_lcdc_tcon1_mode_set(mode, &clk_div, &clk_double, 0, monitor);
|
|
|
|
sunxi_tvencoder_mode_set(monitor);
|
2015-08-03 17:20:26 +00:00
|
|
|
sunxi_composer_enable();
|
2021-02-22 00:12:34 +00:00
|
|
|
lcdc_enable(lcdc, sunxi_display->depth);
|
2017-05-10 16:46:28 +00:00
|
|
|
tvencoder_enable(tve);
|
2014-12-24 11:17:07 +00:00
|
|
|
#endif
|
2014-12-21 13:49:34 +00:00
|
|
|
break;
|
|
|
|
}
|
2014-08-13 05:55:06 +00:00
|
|
|
}
|
|
|
|
|
2014-12-21 13:37:45 +00:00
|
|
|
static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor)
|
|
|
|
{
|
|
|
|
switch (monitor) {
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_dvi: return "dvi";
|
|
|
|
case sunxi_monitor_hdmi: return "hdmi";
|
|
|
|
case sunxi_monitor_lcd: return "lcd";
|
|
|
|
case sunxi_monitor_vga: return "vga";
|
|
|
|
case sunxi_monitor_composite_pal: return "composite-pal";
|
|
|
|
case sunxi_monitor_composite_ntsc: return "composite-ntsc";
|
|
|
|
case sunxi_monitor_composite_pal_m: return "composite-pal-m";
|
|
|
|
case sunxi_monitor_composite_pal_nc: return "composite-pal-nc";
|
2020-04-06 13:06:58 +00:00
|
|
|
case sunxi_monitor_none: /* fall through */
|
|
|
|
default: return "none";
|
2014-12-21 13:37:45 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-03 21:01:38 +00:00
|
|
|
static bool sunxi_has_hdmi(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_VIDEO_HDMI
|
|
|
|
return true;
|
|
|
|
#else
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool sunxi_has_lcd(void)
|
|
|
|
{
|
|
|
|
char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
|
|
|
|
|
|
|
|
return lcd_mode[0] != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool sunxi_has_vga(void)
|
|
|
|
{
|
|
|
|
#if defined CONFIG_VIDEO_VGA || defined CONFIG_VIDEO_VGA_VIA_LCD
|
|
|
|
return true;
|
|
|
|
#else
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2015-08-03 17:20:26 +00:00
|
|
|
static bool sunxi_has_composite(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_VIDEO_COMPOSITE
|
|
|
|
return true;
|
|
|
|
#else
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2015-08-03 21:01:38 +00:00
|
|
|
static enum sunxi_monitor sunxi_get_default_mon(bool allow_hdmi)
|
|
|
|
{
|
|
|
|
if (allow_hdmi && sunxi_has_hdmi())
|
|
|
|
return sunxi_monitor_dvi;
|
|
|
|
else if (sunxi_has_lcd())
|
|
|
|
return sunxi_monitor_lcd;
|
|
|
|
else if (sunxi_has_vga())
|
|
|
|
return sunxi_monitor_vga;
|
2015-08-03 17:20:26 +00:00
|
|
|
else if (sunxi_has_composite())
|
|
|
|
return sunxi_monitor_composite_pal;
|
2015-08-03 21:01:38 +00:00
|
|
|
else
|
|
|
|
return sunxi_monitor_none;
|
|
|
|
}
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
static int sunxi_de_probe(struct udevice *dev)
|
2014-08-13 05:55:06 +00:00
|
|
|
{
|
2021-02-22 00:12:34 +00:00
|
|
|
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
|
|
|
|
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
|
|
|
|
struct sunxi_display_priv *sunxi_display = dev_get_priv(dev);
|
2014-12-19 13:03:40 +00:00
|
|
|
const struct ctfb_res_modes *mode;
|
2014-12-21 15:28:32 +00:00
|
|
|
struct ctfb_res_modes custom;
|
2014-12-19 13:03:40 +00:00
|
|
|
const char *options;
|
2014-12-23 22:04:35 +00:00
|
|
|
#ifdef CONFIG_VIDEO_HDMI
|
2018-12-19 13:06:09 +00:00
|
|
|
int hpd, hpd_delay, edid;
|
|
|
|
bool hdmi_present;
|
2014-12-23 22:04:35 +00:00
|
|
|
#endif
|
2015-08-04 22:06:47 +00:00
|
|
|
int i, overscan_offset, overscan_x, overscan_y;
|
|
|
|
unsigned int fb_dma_addr;
|
2014-12-21 13:37:45 +00:00
|
|
|
char mon[16];
|
2014-12-21 15:28:32 +00:00
|
|
|
char *lcd_mode = CONFIG_VIDEO_LCD_MODE;
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2014-12-21 15:28:32 +00:00
|
|
|
video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode,
|
2021-02-22 00:12:34 +00:00
|
|
|
&sunxi_display->depth, &options);
|
2014-12-23 22:04:35 +00:00
|
|
|
#ifdef CONFIG_VIDEO_HDMI
|
2014-12-19 14:13:57 +00:00
|
|
|
hpd = video_get_option_int(options, "hpd", 1);
|
2014-12-28 08:13:21 +00:00
|
|
|
hpd_delay = video_get_option_int(options, "hpd_delay", 500);
|
2014-12-19 15:05:12 +00:00
|
|
|
edid = video_get_option_int(options, "edid", 1);
|
2014-12-23 22:04:35 +00:00
|
|
|
#endif
|
2015-08-04 22:06:47 +00:00
|
|
|
overscan_x = video_get_option_int(options, "overscan_x", -1);
|
|
|
|
overscan_y = video_get_option_int(options, "overscan_y", -1);
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_get_default_mon(true);
|
2014-12-21 13:37:45 +00:00
|
|
|
video_get_option_string(options, "monitor", mon, sizeof(mon),
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_get_mon_desc(sunxi_display->monitor));
|
2014-12-21 13:37:45 +00:00
|
|
|
for (i = 0; i <= SUNXI_MONITOR_LAST; i++) {
|
|
|
|
if (strcmp(mon, sunxi_get_mon_desc(i)) == 0) {
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = i;
|
2014-12-21 13:37:45 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (i > SUNXI_MONITOR_LAST)
|
|
|
|
printf("Unknown monitor: '%s', falling back to '%s'\n",
|
2021-02-22 00:12:34 +00:00
|
|
|
mon, sunxi_get_mon_desc(sunxi_display->monitor));
|
2014-12-19 13:03:40 +00:00
|
|
|
|
2014-12-25 12:52:04 +00:00
|
|
|
#ifdef CONFIG_VIDEO_HDMI
|
|
|
|
/* If HDMI/DVI is selected do HPD & EDID, and handle fallback */
|
2021-02-22 00:12:34 +00:00
|
|
|
if (sunxi_display->monitor == sunxi_monitor_dvi ||
|
|
|
|
sunxi_display->monitor == sunxi_monitor_hdmi) {
|
2014-12-25 12:52:04 +00:00
|
|
|
/* Always call hdp_detect, as it also enables clocks, etc. */
|
2018-12-19 13:06:09 +00:00
|
|
|
hdmi_present = (sunxi_hdmi_hpd_detect(hpd_delay) == 1);
|
|
|
|
if (hdmi_present && edid) {
|
2014-12-25 12:52:04 +00:00
|
|
|
printf("HDMI connected: ");
|
2021-02-22 00:12:34 +00:00
|
|
|
if (sunxi_hdmi_edid_get_mode(sunxi_display, &custom, true) == 0)
|
2014-12-25 12:52:04 +00:00
|
|
|
mode = &custom;
|
2018-12-19 13:06:09 +00:00
|
|
|
else
|
|
|
|
hdmi_present = false;
|
|
|
|
}
|
|
|
|
/* Fall back to EDID in case HPD failed */
|
|
|
|
if (edid && !hdmi_present) {
|
2021-02-22 00:12:34 +00:00
|
|
|
if (sunxi_hdmi_edid_get_mode(sunxi_display, &custom, false) == 0) {
|
2018-12-19 13:06:09 +00:00
|
|
|
mode = &custom;
|
|
|
|
hdmi_present = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* Shut down when display was not found */
|
|
|
|
if ((hpd || edid) && !hdmi_present) {
|
2014-12-25 12:52:04 +00:00
|
|
|
sunxi_hdmi_shutdown();
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_get_default_mon(false);
|
2014-12-25 12:52:04 +00:00
|
|
|
} /* else continue with hdmi/dvi without a cable connected */
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
switch (sunxi_display->monitor) {
|
2014-12-21 13:49:34 +00:00
|
|
|
case sunxi_monitor_none:
|
2021-02-22 00:12:34 +00:00
|
|
|
printf("Unknown monitor\n");
|
|
|
|
return -EINVAL;
|
2014-12-21 13:49:34 +00:00
|
|
|
case sunxi_monitor_dvi:
|
|
|
|
case sunxi_monitor_hdmi:
|
2015-08-03 21:01:38 +00:00
|
|
|
if (!sunxi_has_hdmi()) {
|
|
|
|
printf("HDMI/DVI not supported on this board\n");
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_monitor_none;
|
|
|
|
return -EINVAL;
|
2015-08-03 21:01:38 +00:00
|
|
|
}
|
2014-12-25 12:52:04 +00:00
|
|
|
break;
|
2014-12-21 13:49:34 +00:00
|
|
|
case sunxi_monitor_lcd:
|
2015-08-03 21:01:38 +00:00
|
|
|
if (!sunxi_has_lcd()) {
|
|
|
|
printf("LCD not supported on this board\n");
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_monitor_none;
|
|
|
|
return -EINVAL;
|
2014-12-21 15:28:32 +00:00
|
|
|
}
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->depth = video_get_params(&custom, lcd_mode);
|
2015-08-03 21:01:38 +00:00
|
|
|
mode = &custom;
|
|
|
|
break;
|
2014-12-21 13:49:34 +00:00
|
|
|
case sunxi_monitor_vga:
|
2015-08-03 21:01:38 +00:00
|
|
|
if (!sunxi_has_vga()) {
|
|
|
|
printf("VGA not supported on this board\n");
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_monitor_none;
|
|
|
|
return -EINVAL;
|
2015-08-03 21:01:38 +00:00
|
|
|
}
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->depth = 18;
|
2014-12-24 11:17:07 +00:00
|
|
|
break;
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_composite_pal:
|
|
|
|
case sunxi_monitor_composite_ntsc:
|
|
|
|
case sunxi_monitor_composite_pal_m:
|
|
|
|
case sunxi_monitor_composite_pal_nc:
|
|
|
|
if (!sunxi_has_composite()) {
|
|
|
|
printf("Composite video not supported on this board\n");
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->monitor = sunxi_monitor_none;
|
|
|
|
return -EINVAL;
|
2015-08-03 17:20:26 +00:00
|
|
|
}
|
2021-02-22 00:12:34 +00:00
|
|
|
if (sunxi_display->monitor == sunxi_monitor_composite_pal ||
|
|
|
|
sunxi_display->monitor == sunxi_monitor_composite_pal_nc)
|
2015-08-03 17:20:26 +00:00
|
|
|
mode = &composite_video_modes[0];
|
|
|
|
else
|
|
|
|
mode = &composite_video_modes[1];
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->depth = 24;
|
2015-08-03 17:20:26 +00:00
|
|
|
break;
|
2014-12-19 15:05:12 +00:00
|
|
|
}
|
|
|
|
|
2015-08-04 22:06:47 +00:00
|
|
|
/* Yes these defaults are quite high, overscan on composite sucks... */
|
|
|
|
if (overscan_x == -1)
|
2021-02-22 00:12:34 +00:00
|
|
|
overscan_x = sunxi_is_composite(sunxi_display->monitor) ? 32 : 0;
|
2015-08-04 22:06:47 +00:00
|
|
|
if (overscan_y == -1)
|
2021-02-22 00:12:34 +00:00
|
|
|
overscan_y = sunxi_is_composite(sunxi_display->monitor) ? 20 : 0;
|
2015-08-04 22:06:47 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->fb_size = plat->size;
|
2015-08-04 22:06:47 +00:00
|
|
|
overscan_offset = (overscan_y * mode->xres + overscan_x) * 4;
|
|
|
|
/* We want to keep the fb_base for simplefb page aligned, where as
|
|
|
|
* the sunxi dma engines will happily accept an unaligned address. */
|
|
|
|
if (overscan_offset)
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->fb_size += 0x1000;
|
2015-02-02 17:00:53 +00:00
|
|
|
|
2015-08-04 22:06:47 +00:00
|
|
|
printf("Setting up a %dx%d%s %s console (overscan %dx%d)\n",
|
|
|
|
mode->xres, mode->yres,
|
2015-08-02 14:49:29 +00:00
|
|
|
(mode->vmode == FB_VMODE_INTERLACED) ? "i" : "",
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_get_mon_desc(sunxi_display->monitor),
|
2015-08-04 22:06:47 +00:00
|
|
|
overscan_x, overscan_y);
|
2015-08-02 14:49:29 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->fb_addr = plat->base;
|
2014-08-13 05:55:06 +00:00
|
|
|
sunxi_engines_init();
|
2015-08-04 22:06:47 +00:00
|
|
|
|
2018-03-03 09:30:17 +00:00
|
|
|
#ifdef CONFIG_EFI_LOADER
|
2021-02-22 00:12:34 +00:00
|
|
|
efi_add_memory_map(sunxi_display->fb_addr, sunxi_display->fb_size,
|
2020-05-17 10:29:19 +00:00
|
|
|
EFI_RESERVED_MEMORY_TYPE);
|
2018-03-03 09:30:17 +00:00
|
|
|
#endif
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
fb_dma_addr = sunxi_display->fb_addr - CONFIG_SYS_SDRAM_BASE;
|
2015-08-04 22:06:47 +00:00
|
|
|
if (overscan_offset) {
|
|
|
|
fb_dma_addr += 0x1000 - (overscan_offset & 0xfff);
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_display->fb_addr += ALIGN(overscan_offset, 0x1000);
|
|
|
|
memset((void *)sunxi_display->fb_addr, 0, sunxi_display->fb_size);
|
|
|
|
flush_cache(sunxi_display->fb_addr, sunxi_display->fb_size);
|
2015-08-04 22:06:47 +00:00
|
|
|
}
|
2021-02-22 00:12:34 +00:00
|
|
|
sunxi_mode_set(sunxi_display, mode, fb_dma_addr);
|
2014-08-13 05:55:06 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
/* The members of struct video_priv to be set by the driver. */
|
|
|
|
uc_priv->bpix = VIDEO_BPP32;
|
|
|
|
uc_priv->xsize = mode->xres;
|
|
|
|
uc_priv->ysize = mode->yres;
|
|
|
|
|
|
|
|
video_set_flush_dcache(dev, true);
|
|
|
|
|
|
|
|
return 0;
|
2014-08-13 05:55:06 +00:00
|
|
|
}
|
2014-08-13 05:55:07 +00:00
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
static int sunxi_de_bind(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
|
|
|
|
|
|
|
|
plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * VNBYTES(LCD_MAX_LOG2_BPP);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct video_ops sunxi_de_ops = {
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(sunxi_de) = {
|
|
|
|
.name = "sunxi_de",
|
|
|
|
.id = UCLASS_VIDEO,
|
|
|
|
.ops = &sunxi_de_ops,
|
|
|
|
.bind = sunxi_de_bind,
|
|
|
|
.probe = sunxi_de_probe,
|
|
|
|
.priv_auto = sizeof(struct sunxi_display_priv),
|
|
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRVINFO(sunxi_de) = {
|
|
|
|
.name = "sunxi_de"
|
|
|
|
};
|
|
|
|
|
2014-08-13 05:55:07 +00:00
|
|
|
/*
|
|
|
|
* Simplefb support.
|
|
|
|
*/
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_VIDEO_DT_SIMPLEFB)
|
|
|
|
int sunxi_simplefb_setup(void *blob)
|
|
|
|
{
|
2021-02-22 00:12:34 +00:00
|
|
|
struct sunxi_display_priv *sunxi_display;
|
|
|
|
struct video_priv *uc_priv;
|
|
|
|
struct udevice *de;
|
2014-08-13 05:55:07 +00:00
|
|
|
int offset, ret;
|
2015-02-02 16:13:29 +00:00
|
|
|
u64 start, size;
|
2014-12-21 15:28:32 +00:00
|
|
|
const char *pipeline = NULL;
|
2014-08-13 05:55:07 +00:00
|
|
|
|
2015-01-19 07:44:07 +00:00
|
|
|
#ifdef CONFIG_MACH_SUN4I
|
|
|
|
#define PIPELINE_PREFIX "de_fe0-"
|
|
|
|
#else
|
|
|
|
#define PIPELINE_PREFIX
|
|
|
|
#endif
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
ret = uclass_find_device_by_name(UCLASS_VIDEO, "sunxi_de", &de);
|
|
|
|
if (ret) {
|
|
|
|
printf("DE not present\n");
|
|
|
|
return 0;
|
|
|
|
} else if (!device_active(de)) {
|
|
|
|
printf("DE is present but not probed\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
uc_priv = dev_get_uclass_priv(de);
|
|
|
|
sunxi_display = dev_get_priv(de);
|
|
|
|
|
|
|
|
switch (sunxi_display->monitor) {
|
2014-12-21 15:28:32 +00:00
|
|
|
case sunxi_monitor_none:
|
|
|
|
return 0;
|
|
|
|
case sunxi_monitor_dvi:
|
|
|
|
case sunxi_monitor_hdmi:
|
2015-01-19 07:44:07 +00:00
|
|
|
pipeline = PIPELINE_PREFIX "de_be0-lcd0-hdmi";
|
2014-12-21 15:28:32 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_lcd:
|
2015-01-19 07:44:07 +00:00
|
|
|
pipeline = PIPELINE_PREFIX "de_be0-lcd0";
|
2014-12-21 15:28:32 +00:00
|
|
|
break;
|
|
|
|
case sunxi_monitor_vga:
|
2014-12-25 12:58:06 +00:00
|
|
|
#ifdef CONFIG_VIDEO_VGA
|
2015-01-19 07:44:07 +00:00
|
|
|
pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
|
2014-12-25 12:58:06 +00:00
|
|
|
#elif defined CONFIG_VIDEO_VGA_VIA_LCD
|
2015-01-19 07:44:07 +00:00
|
|
|
pipeline = PIPELINE_PREFIX "de_be0-lcd0";
|
2014-12-25 12:58:06 +00:00
|
|
|
#endif
|
2014-12-21 15:28:32 +00:00
|
|
|
break;
|
2015-08-03 17:20:26 +00:00
|
|
|
case sunxi_monitor_composite_pal:
|
|
|
|
case sunxi_monitor_composite_ntsc:
|
|
|
|
case sunxi_monitor_composite_pal_m:
|
|
|
|
case sunxi_monitor_composite_pal_nc:
|
|
|
|
pipeline = PIPELINE_PREFIX "de_be0-lcd0-tve0";
|
|
|
|
break;
|
2014-12-21 15:28:32 +00:00
|
|
|
}
|
|
|
|
|
2017-10-26 03:14:45 +00:00
|
|
|
offset = sunxi_simplefb_fdt_match(blob, pipeline);
|
2014-08-13 05:55:07 +00:00
|
|
|
if (offset < 0) {
|
|
|
|
eprintf("Cannot setup simplefb: node not found\n");
|
|
|
|
return 0; /* Keep older kernels working */
|
|
|
|
}
|
|
|
|
|
2015-02-02 16:13:29 +00:00
|
|
|
/*
|
|
|
|
* Do not report the framebuffer as free RAM to the OS, note we cannot
|
|
|
|
* use fdt_add_mem_rsv() here, because then it is still seen as RAM,
|
|
|
|
* and e.g. Linux refuses to iomap RAM on ARM, see:
|
|
|
|
* linux/arch/arm/mm/ioremap.c around line 301.
|
|
|
|
*/
|
|
|
|
start = gd->bd->bi_dram[0].start;
|
2021-02-22 00:12:34 +00:00
|
|
|
size = sunxi_display->fb_addr - start;
|
2015-02-02 16:13:29 +00:00
|
|
|
ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
|
|
|
|
if (ret) {
|
|
|
|
eprintf("Cannot setup simplefb: Error reserving memory\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2021-02-22 00:12:34 +00:00
|
|
|
ret = fdt_setup_simplefb_node(blob, offset, sunxi_display->fb_addr,
|
|
|
|
uc_priv->xsize, uc_priv->ysize,
|
|
|
|
VNBYTES(uc_priv->bpix) * uc_priv->xsize,
|
|
|
|
"x8r8g8b8");
|
2014-08-13 05:55:07 +00:00
|
|
|
if (ret)
|
|
|
|
eprintf("Cannot setup simplefb: Error setting properties\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_OF_BOARD_SETUP && CONFIG_VIDEO_DT_SIMPLEFB */
|