u-boot/arch/arm/dts/rk3588s-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
 */

#include "rockchip-u-boot.dtsi"

/ {
	dmc {
		compatible = "rockchip,rk3588-dmc";
		bootph-all;
		status = "okay";
	};

	usb_host0_ehci: usb@fc800000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfc800000 0x0 0x40000>;
		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
		clock-names = "usbhost", "arbiter";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host0_ohci: usb@fc840000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfc840000 0x0 0x40000>;
		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
		clock-names = "usbhost", "arbiter";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host1_ehci: usb@fc880000 {
		compatible = "generic-ehci";
		reg = <0x0 0xfc880000 0x0 0x40000>;
		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
		clock-names = "usbhost", "arbiter";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	usb_host1_ohci: usb@fc8c0000 {
		compatible = "generic-ohci";
		reg = <0x0 0xfc8c0000 0x0 0x40000>;
		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
		clock-names = "usbhost", "arbiter";
		power-domains = <&power RK3588_PD_USB>;
		status = "disabled";
	};

	pmu1_grf: syscon@fd58a000 {
		bootph-all;
		compatible = "rockchip,rk3588-pmu1-grf", "syscon";
		reg = <0x0 0xfd58a000 0x0 0x2000>;
	};

	usb2phy2_grf: syscon@fd5d8000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
			     "simple-mfd";
		reg = <0x0 0xfd5d8000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy2: usb2-phy@8000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0x8000 0x10>;
			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			status = "disabled";

			u2phy2_host: host-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	usb2phy3_grf: syscon@fd5dc000 {
		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
			     "simple-mfd";
		reg = <0x0 0xfd5dc000 0x0 0x4000>;
		#address-cells = <1>;
		#size-cells = <1>;

		u2phy3: usb2-phy@c000 {
			compatible = "rockchip,rk3588-usb2phy";
			reg = <0xc000 0x10>;
			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
			clock-names = "phyclk";
			#clock-cells = <0>;
			status = "disabled";

			u2phy3_host: host-port {
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	otp: nvmem@fecc0000 {
		compatible = "rockchip,rk3588-otp";
		reg = <0x0 0xfecc0000 0x0 0x400>;
		#address-cells = <1>;
		#size-cells = <1>;
		status = "okay";

		cpu_id: id@7 {
			reg = <0x07 0x10>;
		};
	};

	rng: rng@fe378000 {
		compatible = "rockchip,trngv1";
		reg = <0x0 0xfe378000 0x0 0x200>;
		status = "disabled";
	};
};

&xin24m {
	bootph-all;
	status = "okay";
};

&cru {
	bootph-pre-ram;
	status = "okay";
};

&sys_grf {
	bootph-pre-ram;
	status = "okay";
};

&scmi {
	bootph-pre-ram;
};

&scmi_clk {
	bootph-pre-ram;
};

&sdmmc {
	bootph-pre-ram;
	u-boot,spl-fifo-mode;
};

&sdhci {
	bootph-pre-ram;
	u-boot,spl-fifo-mode;
};

&uart2 {
	clock-frequency = <24000000>;
	bootph-pre-ram;
	status = "okay";
};

&ioc {
	bootph-pre-ram;
};