mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-03 01:50:25 +00:00
3b804b370d
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399 similar to other Rockchip SoCs. Checksum validation fails with: ## Checking hash(es) for Image atf-2 ... sha256 error! Bad hash value for 'hash' hash node in 'atf-2' image node spl_load_simple_fit: can't load image loadables index 1 (ret = -1) mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Add a device tree property, u-boot,spl-fifo-mode, to control when the rockchip_sdhci driver should disable the use of DMA and fallback on PIO mode. Same device tree property is used by the rockchip_dw_mmc driver. In commit2cc6cde647("mmc: rockchip_sdhci: Limit number of blocks read in a single command") the DMA mode was disabled using a CONFIG option on RK3588. Revert that and instead disable DMA using the device tree property for all RK3588 boards, also apply similar workaround for all RK3399 boards. Fixes:2cc6cde647("mmc: rockchip_sdhci: Limit number of blocks read in a single command") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Quentin Schulz <foss+uboot@0leil.net> # RK3399 Puma, RK3588 Tiger
167 lines
3.4 KiB
Text
167 lines
3.4 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#include "rockchip-u-boot.dtsi"
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/ {
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dmc {
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compatible = "rockchip,rk3588-dmc";
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bootph-all;
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status = "okay";
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};
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usb_host0_ehci: usb@fc800000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host0_ohci: usb@fc840000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfc840000 0x0 0x40000>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host1_ehci: usb@fc880000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfc880000 0x0 0x40000>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host1_ohci: usb@fc8c0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfc8c0000 0x0 0x40000>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
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clock-names = "usbhost", "arbiter";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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pmu1_grf: syscon@fd58a000 {
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bootph-all;
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compatible = "rockchip,rk3588-pmu1-grf", "syscon";
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reg = <0x0 0xfd58a000 0x0 0x2000>;
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};
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usb2phy2_grf: syscon@fd5d8000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5d8000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy2: usb2-phy@8000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x8000 0x10>;
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interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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u2phy2_host: host-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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usb2phy3_grf: syscon@fd5dc000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5dc000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy3: usb2-phy@c000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0xc000 0x10>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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u2phy3_host: host-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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otp: nvmem@fecc0000 {
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compatible = "rockchip,rk3588-otp";
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reg = <0x0 0xfecc0000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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cpu_id: id@7 {
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reg = <0x07 0x10>;
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};
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};
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rng: rng@fe378000 {
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compatible = "rockchip,trngv1";
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reg = <0x0 0xfe378000 0x0 0x200>;
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status = "disabled";
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};
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};
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&xin24m {
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bootph-all;
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status = "okay";
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};
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&cru {
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bootph-pre-ram;
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status = "okay";
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};
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&sys_grf {
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bootph-pre-ram;
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status = "okay";
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};
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&scmi {
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bootph-pre-ram;
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};
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&scmi_clk {
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bootph-pre-ram;
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};
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&sdmmc {
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bootph-pre-ram;
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u-boot,spl-fifo-mode;
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};
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&sdhci {
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bootph-pre-ram;
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u-boot,spl-fifo-mode;
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};
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&uart2 {
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clock-frequency = <24000000>;
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bootph-pre-ram;
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status = "okay";
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};
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&ioc {
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bootph-pre-ram;
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};
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