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u-boot/arch/x86/cpu/intel_common/Makefile

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SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-06 21:58:06 +00:00
# SPDX-License-Identifier: GPL-2.0+
x86: Move cache-as-RAM code into a common location This cache-as-RAM (CAR) code is common to several Intel chips. Create a new intel_common directory and move it in there. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:06:53 +00:00
#
# Copyright (c) 2016 Google, Inc
x86: acpi: Add common Intel ACPI tables Add various tables that are common to Intel CPUs. These functions can be used by arch-specific CPU code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 18:45:14 +00:00
obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o
x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:03:46 +00:00
ifdef CONFIG_HAVE_MRC
x86: Allow 16-bit init to be in TPL At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:53 +00:00
obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o
x86: Support TPL in Intel common code Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:59:05 +00:00
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:03:46 +00:00
endif
x86: Add support for newer CAR schemes Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:25 +00:00
x86: apl: Support writing the IntelGraphicsMem table This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-09-22 18:45:03 +00:00
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
endif
x86: Add support for newer CAR schemes Newer Intel SoCs have different ways of setting up cache-as-ram (CAR). Add support for these along with suitable configuration options. To make the code cleaner, adjust a few definitions in processor.h so that they can be used from assembler. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:25 +00:00
ifdef CONFIG_INTEL_CAR_CQOS
obj-$(CONFIG_TPL_BUILD) += car2.o
ifndef CONFIG_SPL_BUILD
obj-y += car2_uninit.o
endif
endif
x86: Move common CPU code to its own place Some of the Intel CPU code is common to several Intel CPUs. Move it into a common location along with required declarations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:06:58 +00:00
obj-y += cpu.o
x86: spi: Add helper functions for Intel Fast SPI Most x86 CPUs use a mechanism where the SPI flash is mapped into the very top of 32-bit address space, so that it can be executed in place and read simply by copying from memory. For an 8MB ROM the mapping starts at 0xff800000. However some recent Intel CPUs do not use a simple 1:1 memory map. Instead the map starts at a different address and not all of the SPI flash is accessible through the map. This 'Fast SPI' feature requires that U-Boot check the location of the map. It is also possible (optionally) to read from the SPI flash using a driver. Add support for booting from Fast SPI. The memory-mapped version is used by both TPL and SPL on Apollo Lake. In respect of a SPI flash driver, the actual SPI driver is ich.c - this just adds a few helper functions and definitions. This is used by Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:41:43 +00:00
obj-y += fast_spi.o
x86: Move common LPC code to its own place Some of the LPC code is common to several Intel LPC devices. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:06:57 +00:00
obj-y += lpc.o
x86: Add low-power subsystem (lpss) support This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 04:42:52 +00:00
obj-y += lpss.o
x86: apl: Reduce size for TPL Update various drivers to use of_match_ptr() and to avoid including debug strings in TPL. Omit the WiFi driver entirely, since it is not used in TPL. This reduces the TPL binary size by about 608 bytes. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-23 15:11:30 +00:00
obj-$(CONFIG_$(SPL_)INTEL_GENERIC_WIFI) += generic_wifi.o
x86: Create a 32/64-bit selection for the app Most EFI implementations use 64-bit but U-Boot only supports running as a 32-bit app at present. While efi-x86_payload64 does boot from 64-bit UEFI it immediately changes back to 32-bit before starting U-Boot. In order to support a 64-bit U-Boot app, update the Kconfig to add an option for 32/64 bit. Update the prompt for the existing option so it is clear it relates to the stub. Move both up to just under the choice that controls them, since this looks better and the menu. Use CONFIG_EFI_APP in the Makefile instead of CONFIG_TARGET_EFI_APP, since the latter is specific to a single target and we will have two. Memory size is set to 32MB for now so that it can run on qemu without increasing the default memory size. We may need to increase the default later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-04 03:09:06 +00:00
ifndef CONFIG_EFI_APP
x86: Support TPL in Intel common code Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:59:05 +00:00
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
x86: Move microcode code to a common location This code is used on several Intel CPUs. Move it into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:06:54 +00:00
obj-y += microcode.o
endif
x86: Support TPL in Intel common code Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:59:05 +00:00
endif
x86: Move common PCH code into a common place The SATA indexed register write functions are common to several Intel PCHs. Move this into a common location. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-16 13:44:36 +00:00
obj-y += pch.o
x86: itss: Add a Kconfig option to enable/disable ITSS driver Add a Kconfig option to support enabling/disabling the inclusion of the ITSS driver depending on the platform. Atuomatically select the ITSS driver when building for Apollo Lake. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed in http://patchwork.ozlabs.org/patch/1232761/] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-03 13:06:45 +00:00
obj-$(CONFIG_HAVE_ITSS) += itss.o
x86: Move P2SB from Apollo Lake to a more generic location The Primary to Sideband Bridge (P2SB) is not specific to Apollo Lake, so move its driver to a common location within arch/x86. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-02-04 08:04:56 +00:00
obj-$(CONFIG_HAVE_P2SB) += p2sb.o
x86: Add common Intel code for SPL Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:56 +00:00
ifdef CONFIG_SPL
ifndef CONFIG_SPL_BUILD
x86: coreboot: Allow building an SPL image Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-01 03:21:43 +00:00
ifndef CONFIG_SYS_COREBOOT
x86: Add common Intel code for SPL Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 03:58:56 +00:00
obj-y += cpu_from_spl.o
endif
endif
x86: coreboot: Allow building an SPL image Make a few adjustments to allow us to build an SPL image for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-01 03:21:43 +00:00
endif
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