2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0 */
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2017-04-25 18:44:36 +00:00
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#ifndef _MISC_H_
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#define _MISC_H_
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2018-10-10 12:55:23 +00:00
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#include <asm/sections.h>
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2017-04-25 18:44:36 +00:00
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void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
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struct bsel {
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const char *mode;
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const char *name;
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};
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extern struct bsel bsel_str[];
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#ifdef CONFIG_FPGA
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2018-12-20 02:35:15 +00:00
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void socfpga_fpga_add(void *fpga_desc);
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2017-04-25 18:44:36 +00:00
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#else
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2018-12-20 02:35:15 +00:00
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inline void socfpga_fpga_add(void *fpga_desc) {}
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2017-04-25 18:44:36 +00:00
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#endif
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2018-08-13 19:34:35 +00:00
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#ifdef CONFIG_TARGET_SOCFPGA_GEN5
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void socfpga_sdram_remap_zero(void);
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2018-10-10 12:55:23 +00:00
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static inline bool socfpga_is_booting_from_fpga(void)
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{
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if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
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(__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
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return true;
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return false;
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}
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2018-08-13 19:34:35 +00:00
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#endif
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2018-08-18 17:11:52 +00:00
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#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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void socfpga_init_security_policies(void);
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void socfpga_sdram_remap_zero(void);
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#endif
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2019-04-16 20:28:08 +00:00
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void do_bridge_reset(int enable, unsigned int mask);
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2018-05-23 16:17:23 +00:00
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2017-04-25 18:44:36 +00:00
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#endif /* _MISC_H_ */
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