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u-boot/drivers/reset/Kconfig

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Add a reset driver framework/uclass A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:43:58 +00:00
menu "Reset Controller Support"
config DM_RESET
bool "Enable reset controllers using Driver Model"
depends on DM && OF_CONTROL
help
Enable support for the reset controller driver class. Many hardware
modules are equipped with a reset signal, typically driven by some
reset controller hardware module within the chip. In U-Boot, reset
controller drivers allow control over these reset signals. In some
cases this API is applicable to chips outside the CPU as well,
although driving such reset isgnals using GPIOs may be more
appropriate in this case.
reset: implement a reset test This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:43:59 +00:00
config SANDBOX_RESET
bool "Enable the sandbox reset test driver"
depends on DM_MAILBOX && SANDBOX
help
Enable support for a test reset controller implementation, which
simply accepts requests to reset various HW modules without actually
doing anything beyond a little error checking.
reset: Add STi reset support This patch adds a reset controller implementation for STMicroelectronics STi family SoCs; it allows a group of related reset like controls found in multiple system configuration registers to be represented by a single controller device. Driver code has been mainly extracted from kernel drivers/reset/sti/reset-stih407.c Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-03-22 09:54:03 +00:00
config STI_RESET
bool "Enable the STi reset"
depends on ARCH_STI
help
Support for reset controllers on STMicroelectronics STiH407 family SoCs.
Say Y if you want to control reset signals provided by system config
block.
dm: reset: add stm32 reset driver This driver is adapted from linux drivers/reset/reset-stm32.c It's compatible with STM32 F4/F7/H7 SoCs. This driver doesn't implement .of_match as it's binded by MFD RCC driver. To add support for each SoC family, a SoC's specific include/dt-binfings/mfd/stm32xx-rcc.h file must be added. This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs. Other SoCs support will be added in the future. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-09-13 16:00:07 +00:00
config STM32_RESET
bool "Enable the STM32 reset"
depends on STM32
help
Support for reset controllers on STMicroelectronics STM32 family SoCs.
This resset driver is compatible with STM32 F4/F7 and H7 SoCs.
reset: implement a driver for the Tegra CAR Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-09-13 16:45:58 +00:00
config TEGRA_CAR_RESET
bool "Enable Tegra CAR-based reset driver"
depends on TEGRA_CAR
help
Enable support for manipulating Tegra's on-SoC reset signals via
direct register access to the Tegra CAR (Clock And Reset controller).
reset: add Tegra186 reset driver In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-08 17:28:25 +00:00
config TEGRA186_RESET
bool "Enable Tegra186 BPMP-based reset driver"
depends on TEGRA186_BPMP
help
Enable support for manipulating Tegra's on-SoC reset signals via IPC
requests to the BPMP (Boot and Power Management Processor).
dm: reset: add BCM6345 reset driver This is a simplified version of linux/arch/mips/bcm63xx/reset.c Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-03 13:10:21 +00:00
config RESET_BCM6345
bool "Reset controller driver for BCM6345"
depends on DM_RESET && ARCH_BMIPS
help
Support reset controller on BCM6345.
reset: uniphier: add reset controller driver for UniPhier SoCs This is the initial commit for UniPhier reset controller driver. Most code was ported from Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-08 04:25:31 +00:00
config RESET_UNIPHIER
bool "Reset controller driver for UniPhier SoCs"
depends on ARCH_UNIPHIER
default y
help
Support for reset controllers on UniPhier SoCs.
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
aspeed: Reset Driver Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to perform resets and thus depends on it. The actual Watchdog device used needs to be configured in Device Tree using "aspeed,wdt" property, which must be WDT phandle, for example: rst: reset-controller { compatible = "aspeed,ast2500-reset"; aspeed,wdt = <&wdt1>; } Signed-off-by: Maxim Sloyko <maxims@google.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-17 19:00:24 +00:00
config AST2500_RESET
bool "Reset controller driver for AST2500 SoCs"
depends on DM_RESET && WDT_ASPEED
default y if ASPEED_AST2500
help
Support for reset controller on AST2500 SoC. This controller uses
watchdog to reset different peripherals and thus only supports
resets that are supported by watchdog. The main limitation though
is that some reset signals, like I2C or MISC reset multiple devices.
Add a reset driver framework/uclass A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-06-17 15:43:58 +00:00
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