u-boot/drivers/reset/Kconfig

menu "Reset Controller Support"

config DM_RESET
	bool "Enable reset controllers using Driver Model"
	depends on DM && OF_CONTROL
	help
	  Enable support for the reset controller driver class. Many hardware
	  modules are equipped with a reset signal, typically driven by some
	  reset controller hardware module within the chip. In U-Boot, reset
	  controller drivers allow control over these reset signals. In some
	  cases this API is applicable to chips outside the CPU as well,
	  although driving such reset isgnals using GPIOs may be more
	  appropriate in this case.

config SANDBOX_RESET
	bool "Enable the sandbox reset test driver"
	depends on DM_MAILBOX && SANDBOX
	help
	  Enable support for a test reset controller implementation, which
	  simply accepts requests to reset various HW modules without actually
	  doing anything beyond a little error checking.

config TEGRA_CAR_RESET
	bool "Enable Tegra CAR-based reset driver"
	depends on TEGRA_CAR
	help
	  Enable support for manipulating Tegra's on-SoC reset signals via
	  direct register access to the Tegra CAR (Clock And Reset controller).

config TEGRA186_RESET
	bool "Enable Tegra186 BPMP-based reset driver"
	depends on TEGRA186_BPMP
	help
	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
	  requests to the BPMP (Boot and Power Management Processor).

endmenu
Add a reset driver framework/uclass A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> 2016-06-17 15:43:58 +00:00			`menu "Reset Controller Support"`

			`config DM_RESET`
			`bool "Enable reset controllers using Driver Model"`
			`depends on DM && OF_CONTROL`
			`help`
			`Enable support for the reset controller driver class. Many hardware`
			`modules are equipped with a reset signal, typically driven by some`
			`reset controller hardware module within the chip. In U-Boot, reset`
			`controller drivers allow control over these reset signals. In some`
			`cases this API is applicable to chips outside the CPU as well,`
			`although driving such reset isgnals using GPIOs may be more`
			`appropriate in this case.`

reset: implement a reset test This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> 2016-06-17 15:43:59 +00:00			`config SANDBOX_RESET`
			`bool "Enable the sandbox reset test driver"`
			`depends on DM_MAILBOX && SANDBOX`
			`help`
			`Enable support for a test reset controller implementation, which`
			`simply accepts requests to reset various HW modules without actually`
			`doing anything beyond a little error checking.`

reset: implement a driver for the Tegra CAR Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> 2016-09-13 16:45:58 +00:00			`config TEGRA_CAR_RESET`
			`bool "Enable Tegra CAR-based reset driver"`
			`depends on TEGRA_CAR`
			`help`
			`Enable support for manipulating Tegra's on-SoC reset signals via`
			`direct register access to the Tegra CAR (Clock And Reset controller).`

reset: add Tegra186 reset driver In Tegra186, on-SoC reset signals are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> 2016-08-08 17:28:25 +00:00			`config TEGRA186_RESET`
			`bool "Enable Tegra186 BPMP-based reset driver"`
			`depends on TEGRA186_BPMP`
			`help`
			`Enable support for manipulating Tegra's on-SoC reset signals via IPC`
			`requests to the BPMP (Boot and Power Management Processor).`

Add a reset driver framework/uclass A reset controller is a hardware module that controls reset signals that affect other hardware modules or chips. This patch defines a standard API that connects reset clients (i.e. the drivers for devices affected by reset signals) to drivers for reset controllers/providers. Initially, DT is the only supported method for connecting the two. The DT binding specification (reset.txt) was taken from Linux kernel v4.5's Documentation/devicetree/bindings/reset/reset.txt. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> 2016-06-17 15:43:58 +00:00			`endmenu`