2003-10-15 23:53:47 +00:00
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/*
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2009-03-19 07:53:01 +00:00
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* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
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2003-10-15 23:53:47 +00:00
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* Copyright (C) 2003 Motorola,Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
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*
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* The processor starts at 0xfffffffc and the code is first executed in the
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* last 4K page(0xfffff000-0xffffffff) in flash/rom.
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*
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*/
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#include <config.h>
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#include <mpc85xx.h>
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2008-11-03 15:30:59 +00:00
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#include <timestamp.h>
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2003-10-15 23:53:47 +00:00
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#include <version.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#ifndef CONFIG_IDENT_STRING
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#define CONFIG_IDENT_STRING ""
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#endif
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#undef MSR_KERNEL
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2007-08-14 06:34:21 +00:00
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#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
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2003-10-15 23:53:47 +00:00
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/*
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* Set up GOT: Global Offset Table
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*
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* Use r14 to access the GOT
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*/
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START_GOT
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GOT_ENTRY(_GOT2_TABLE_)
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GOT_ENTRY(_FIXUP_TABLE_)
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ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
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#ifndef CONFIG_NAND_SPL
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2003-10-15 23:53:47 +00:00
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GOT_ENTRY(_start)
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GOT_ENTRY(_start_of_vectors)
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GOT_ENTRY(_end_of_vectors)
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GOT_ENTRY(transfer_to_handler)
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ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
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#endif
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2003-10-15 23:53:47 +00:00
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GOT_ENTRY(__init_end)
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GOT_ENTRY(_end)
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GOT_ENTRY(__bss_start)
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END_GOT
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/*
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* e500 Startup -- after reset only the last 4KB of the effective
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* address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
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* section is located at THIS LAST page and basically does three
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* things: clear some registers, set up exception tables and
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* add more TLB entries for 'larger spaces'(e.g. the boot rom) to
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* continue the boot procedure.
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* Once the boot rom is mapped by TLB entries we can proceed
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* with normal startup.
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*
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*/
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2007-08-14 06:34:21 +00:00
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.section .bootpg,"ax"
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.globl _start_e500
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2003-10-15 23:53:47 +00:00
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_start_e500:
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2004-06-09 00:34:46 +00:00
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2007-08-14 06:34:21 +00:00
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/* clear registers/arrays not reset by hardware */
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2003-10-15 23:53:47 +00:00
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2007-08-14 06:34:21 +00:00
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/* L1 */
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li r0,2
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mtspr L1CSR0,r0 /* invalidate d-cache */
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2008-05-20 14:00:29 +00:00
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mtspr L1CSR1,r0 /* invalidate i-cache */
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2003-10-15 23:53:47 +00:00
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mfspr r1,DBSR
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mtspr DBSR,r1 /* Clear all valid bits */
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2007-08-14 06:34:21 +00:00
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/*
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* Enable L1 Caches early
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*
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*/
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2003-10-15 23:53:47 +00:00
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2009-03-19 07:53:01 +00:00
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#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
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/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
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li r2,(32 + 0)
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mtspr L1CSR2,r2
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#endif
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2007-08-14 06:34:21 +00:00
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lis r2,L1CSR0_CPE@H /* enable parity */
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ori r2,r2,L1CSR0_DCE
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mtspr L1CSR0,r2 /* enable L1 Dcache */
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isync
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mtspr L1CSR1,r2 /* enable L1 Icache */
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2003-10-15 23:53:47 +00:00
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isync
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2007-08-14 06:34:21 +00:00
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msync
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2003-10-15 23:53:47 +00:00
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/* Setup interrupt vectors */
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2005-05-13 22:49:36 +00:00
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lis r1,TEXT_BASE@h
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2007-08-14 06:34:21 +00:00
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mtspr IVPR,r1
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2003-10-15 23:53:47 +00:00
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2005-05-13 22:49:36 +00:00
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li r1,0x0100
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2003-10-15 23:53:47 +00:00
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mtspr IVOR0,r1 /* 0: Critical input */
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2005-05-13 22:49:36 +00:00
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li r1,0x0200
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2003-10-15 23:53:47 +00:00
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mtspr IVOR1,r1 /* 1: Machine check */
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2005-05-13 22:49:36 +00:00
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li r1,0x0300
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2003-10-15 23:53:47 +00:00
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mtspr IVOR2,r1 /* 2: Data storage */
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2005-05-13 22:49:36 +00:00
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li r1,0x0400
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2003-10-15 23:53:47 +00:00
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mtspr IVOR3,r1 /* 3: Instruction storage */
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li r1,0x0500
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mtspr IVOR4,r1 /* 4: External interrupt */
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li r1,0x0600
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mtspr IVOR5,r1 /* 5: Alignment */
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li r1,0x0700
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mtspr IVOR6,r1 /* 6: Program check */
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li r1,0x0800
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mtspr IVOR7,r1 /* 7: floating point unavailable */
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2005-05-13 22:49:36 +00:00
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li r1,0x0900
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2003-10-15 23:53:47 +00:00
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mtspr IVOR8,r1 /* 8: System call */
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/* 9: Auxiliary processor unavailable(unsupported) */
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2005-05-13 22:49:36 +00:00
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li r1,0x0a00
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2003-10-15 23:53:47 +00:00
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mtspr IVOR10,r1 /* 10: Decrementer */
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2005-05-13 22:49:36 +00:00
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li r1,0x0b00
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mtspr IVOR11,r1 /* 11: Interval timer */
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li r1,0x0c00
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2005-08-03 23:24:19 +00:00
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mtspr IVOR12,r1 /* 12: Watchdog timer */
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li r1,0x0d00
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2003-10-15 23:53:47 +00:00
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mtspr IVOR13,r1 /* 13: Data TLB error */
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2005-05-13 22:49:36 +00:00
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li r1,0x0e00
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2003-10-15 23:53:47 +00:00
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mtspr IVOR14,r1 /* 14: Instruction TLB error */
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2005-05-13 22:49:36 +00:00
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li r1,0x0f00
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2003-10-15 23:53:47 +00:00
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mtspr IVOR15,r1 /* 15: Debug */
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/* Clear and set up some registers. */
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2008-01-17 04:38:34 +00:00
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li r0,0x0000
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2003-10-15 23:53:47 +00:00
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lis r1,0xffff
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mtspr DEC,r0 /* prevent dec exceptions */
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mttbl r0 /* prevent fit & wdt exceptions */
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mttbu r0
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mtspr TSR,r1 /* clear all timer exception status */
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mtspr TCR,r0 /* disable all */
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mtspr ESR,r0 /* clear exception syndrome register */
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mtspr MCSR,r0 /* machine check syndrome register */
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mtxer r0 /* clear integer exception register */
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2009-08-20 22:45:05 +00:00
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#ifdef CONFIG_SYS_BOOK3E_HV
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mtspr MAS8,r0 /* make sure MAS8 is clear */
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#endif
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2003-10-15 23:53:47 +00:00
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/* Enable Time Base and Select Time Base Clock */
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2004-07-09 23:27:13 +00:00
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lis r0,HID0_EMCP@h /* Enable machine check */
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2005-07-25 19:05:07 +00:00
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#if defined(CONFIG_ENABLE_36BIT_PHYS)
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2008-01-17 04:38:34 +00:00
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ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
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2005-07-25 19:05:07 +00:00
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#endif
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2009-03-19 14:16:10 +00:00
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#ifndef CONFIG_E500MC
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2008-01-17 04:38:34 +00:00
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ori r0,r0,HID0_TBEN@l /* Enable Timebase */
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2009-03-19 14:16:10 +00:00
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#endif
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2003-10-15 23:53:47 +00:00
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mtspr HID0,r0
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2008-10-23 06:47:38 +00:00
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#ifndef CONFIG_E500MC
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2007-08-14 06:34:21 +00:00
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li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
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2003-10-15 23:53:47 +00:00
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mtspr HID1,r0
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2008-10-23 06:47:38 +00:00
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#endif
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2003-10-15 23:53:47 +00:00
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/* Enable Branch Prediction */
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#if defined(CONFIG_BTB)
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li r0,0x201 /* BBFI = 1, BPEN = 1 */
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mtspr BUCSR,r0
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#endif
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2008-10-16 13:01:15 +00:00
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#if defined(CONFIG_SYS_INIT_DBCR)
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2003-10-15 23:53:47 +00:00
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lis r1,0xffff
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ori r1,r1,0xffff
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2004-07-09 23:27:13 +00:00
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mtspr DBSR,r1 /* Clear all status bits */
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2008-10-16 13:01:15 +00:00
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lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
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ori r0,r0,CONFIG_SYS_INIT_DBCR@l
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2004-07-09 23:27:13 +00:00
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mtspr DBCR0,r0
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2003-10-15 23:53:47 +00:00
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#endif
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2009-03-27 21:02:44 +00:00
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#ifdef CONFIG_MPC8569
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#define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
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#define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
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/* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
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* use address space which is more than 12bits, and it must be done in
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* the 4K boot page. So we set this bit here.
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*/
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/* create a temp mapping TLB0[0] for LBCR */
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lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
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ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
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lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
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ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
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lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
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ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
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lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))@h
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ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))@l
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mtspr MAS0,r6
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mtspr MAS1,r7
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mtspr MAS2,r8
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mtspr MAS3,r9
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isync
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msync
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tlbwe
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/* Set LBCR register */
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lis r4,CONFIG_SYS_LBCR_ADDR@h
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ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
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lis r5,CONFIG_SYS_LBC_LBCR@h
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ori r5,r5,CONFIG_SYS_LBC_LBCR@l
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stw r5,0(r4)
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isync
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/* invalidate this temp TLB */
|
|
|
|
|
lis r4,CONFIG_SYS_LBC_ADDR@h
|
|
|
|
|
ori r4,r4,CONFIG_SYS_LBC_ADDR@l
|
|
|
|
|
tlbivax 0,r4
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
#endif /* CONFIG_MPC8569 */
|
|
|
|
|
|
2008-01-17 04:38:34 +00:00
|
|
|
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
|
|
|
|
|
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
|
|
|
|
|
|
ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
|
|
|
#ifndef CONFIG_SYS_RAMBOOT
|
|
|
|
|
/* create a temp mapping in AS=1 to the 4M boot window */
|
2008-12-16 04:09:27 +00:00
|
|
|
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
|
|
|
|
|
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
|
2008-01-17 04:38:34 +00:00
|
|
|
|
2008-12-16 04:09:27 +00:00
|
|
|
lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
|
|
|
|
|
ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
|
2008-01-17 04:38:34 +00:00
|
|
|
|
2008-12-16 04:09:27 +00:00
|
|
|
/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
|
|
|
|
|
lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
|
|
|
|
|
ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
|
|
|
#else
|
|
|
|
|
/*
|
|
|
|
|
* create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
|
|
|
|
|
* image has been relocated to TEXT_BASE on the second stage.
|
|
|
|
|
*/
|
|
|
|
|
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
|
|
|
|
|
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
|
|
|
|
|
|
|
|
|
|
lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
|
|
|
|
|
ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
|
|
|
|
|
|
|
|
|
|
lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
|
|
|
|
|
ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
|
|
|
|
#endif
|
2008-01-17 04:38:34 +00:00
|
|
|
|
|
|
|
|
mtspr MAS0,r6
|
|
|
|
|
mtspr MAS1,r7
|
|
|
|
|
mtspr MAS2,r8
|
|
|
|
|
mtspr MAS3,r9
|
|
|
|
|
isync
|
|
|
|
|
msync
|
|
|
|
|
tlbwe
|
|
|
|
|
|
|
|
|
|
/* create a temp mapping in AS=1 to the stack */
|
|
|
|
|
lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
|
|
|
|
|
ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
|
|
|
|
|
|
|
|
|
|
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
|
|
|
|
|
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
|
|
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
|
|
|
|
|
ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
|
2008-01-17 04:38:34 +00:00
|
|
|
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
|
|
|
|
|
ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
|
2008-01-17 04:38:34 +00:00
|
|
|
|
|
|
|
|
mtspr MAS0,r6
|
|
|
|
|
mtspr MAS1,r7
|
|
|
|
|
mtspr MAS2,r8
|
|
|
|
|
mtspr MAS3,r9
|
|
|
|
|
isync
|
|
|
|
|
msync
|
|
|
|
|
tlbwe
|
|
|
|
|
|
2009-08-20 22:44:20 +00:00
|
|
|
lis r6,MSR_IS|MSR_DS@h
|
|
|
|
|
ori r6,r6,MSR_IS|MSR_DS@l
|
2008-01-17 04:38:34 +00:00
|
|
|
lis r7,switch_as@h
|
|
|
|
|
ori r7,r7,switch_as@l
|
|
|
|
|
|
|
|
|
|
mtspr SPRN_SRR0,r7
|
|
|
|
|
mtspr SPRN_SRR1,r6
|
|
|
|
|
rfi
|
|
|
|
|
|
|
|
|
|
switch_as:
|
2007-08-07 23:07:27 +00:00
|
|
|
/* L1 DCache is used for initial RAM */
|
|
|
|
|
|
|
|
|
|
/* Allocate Initial RAM in data cache.
|
|
|
|
|
*/
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
|
|
|
|
|
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
|
2008-01-08 07:22:21 +00:00
|
|
|
mfspr r2, L1CFG0
|
|
|
|
|
andi. r2, r2, 0x1ff
|
|
|
|
|
/* cache size * 1024 / (2 * L1 line size) */
|
|
|
|
|
slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
|
2007-08-07 23:07:27 +00:00
|
|
|
mtctr r2
|
|
|
|
|
li r0,0
|
|
|
|
|
1:
|
|
|
|
|
dcbz r0,r3
|
|
|
|
|
dcbtls 0,r0,r3
|
2008-10-16 13:01:15 +00:00
|
|
|
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
|
2007-08-07 23:07:27 +00:00
|
|
|
bdnz 1b
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
/* Jump out the last 4K page and continue to 'normal' start */
|
2008-10-16 13:01:15 +00:00
|
|
|
#ifdef CONFIG_SYS_RAMBOOT
|
2007-08-14 06:34:21 +00:00
|
|
|
b _start_cont
|
2007-08-07 23:07:27 +00:00
|
|
|
#else
|
|
|
|
|
/* Calculate absolute address in FLASH and jump there */
|
|
|
|
|
/*--------------------------------------------------------------*/
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3,CONFIG_SYS_MONITOR_BASE@h
|
|
|
|
|
ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
|
2007-08-07 23:07:27 +00:00
|
|
|
addi r3,r3,_start_cont - _start + _START_OFFSET
|
|
|
|
|
mtlr r3
|
2007-09-24 17:36:01 +00:00
|
|
|
blr
|
2007-08-07 23:07:27 +00:00
|
|
|
#endif
|
2007-08-14 06:34:21 +00:00
|
|
|
|
|
|
|
|
.text
|
|
|
|
|
.globl _start
|
|
|
|
|
_start:
|
|
|
|
|
.long 0x27051956 /* U-BOOT Magic Number */
|
|
|
|
|
.globl version_string
|
|
|
|
|
version_string:
|
|
|
|
|
.ascii U_BOOT_VERSION
|
2008-11-03 15:30:59 +00:00
|
|
|
.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
|
2007-08-14 06:34:21 +00:00
|
|
|
.ascii CONFIG_IDENT_STRING, "\0"
|
|
|
|
|
|
|
|
|
|
.align 4
|
|
|
|
|
.globl _start_cont
|
|
|
|
|
_start_cont:
|
2003-10-15 23:53:47 +00:00
|
|
|
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
|
|
|
|
|
ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
li r0,0
|
|
|
|
|
stwu r0,-4(r1)
|
|
|
|
|
stwu r0,-4(r1) /* Terminate call chain */
|
|
|
|
|
|
|
|
|
|
stwu r1,-8(r1) /* Save back chain and move SP */
|
|
|
|
|
lis r0,RESET_VECTOR@h /* Address of reset vector */
|
2007-08-14 06:34:21 +00:00
|
|
|
ori r0,r0,RESET_VECTOR@l
|
2003-10-15 23:53:47 +00:00
|
|
|
stwu r1,-8(r1) /* Save back chain and move SP */
|
|
|
|
|
stw r0,+12(r1) /* Save return addr (underflow vect) */
|
|
|
|
|
|
|
|
|
|
GET_GOT
|
2008-01-17 04:38:34 +00:00
|
|
|
bl cpu_init_early_f
|
|
|
|
|
|
|
|
|
|
/* switch back to AS = 0 */
|
|
|
|
|
lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
|
|
|
|
|
ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
|
|
|
|
|
mtmsr r3
|
|
|
|
|
isync
|
|
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
bl cpu_init_f
|
|
|
|
|
bl board_init_f
|
2004-07-09 23:27:13 +00:00
|
|
|
isync
|
2003-10-15 23:53:47 +00:00
|
|
|
|
ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
|
|
|
#ifndef CONFIG_NAND_SPL
|
2007-08-14 06:34:21 +00:00
|
|
|
. = EXC_OFF_SYS_RESET
|
2003-10-15 23:53:47 +00:00
|
|
|
.globl _start_of_vectors
|
|
|
|
|
_start_of_vectors:
|
2007-08-14 06:34:21 +00:00
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
/* Critical input. */
|
2007-08-14 06:34:21 +00:00
|
|
|
CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
|
|
|
|
|
|
|
|
|
|
/* Machine check */
|
|
|
|
|
MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/* Data Storage exception. */
|
|
|
|
|
STD_EXCEPTION(0x0300, DataStorage, UnknownException)
|
|
|
|
|
|
|
|
|
|
/* Instruction Storage exception. */
|
|
|
|
|
STD_EXCEPTION(0x0400, InstStorage, UnknownException)
|
|
|
|
|
|
|
|
|
|
/* External Interrupt exception. */
|
2007-08-14 06:34:21 +00:00
|
|
|
STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/* Alignment exception. */
|
|
|
|
|
. = 0x0600
|
|
|
|
|
Alignment:
|
2007-06-22 12:58:04 +00:00
|
|
|
EXCEPTION_PROLOG(SRR0, SRR1)
|
2003-10-15 23:53:47 +00:00
|
|
|
mfspr r4,DAR
|
|
|
|
|
stw r4,_DAR(r21)
|
|
|
|
|
mfspr r5,DSISR
|
|
|
|
|
stw r5,_DSISR(r21)
|
|
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
li r20,MSR_KERNEL
|
|
|
|
|
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
|
|
|
|
|
lwz r6,GOT(transfer_to_handler)
|
|
|
|
|
mtlr r6
|
|
|
|
|
blrl
|
|
|
|
|
.L_Alignment:
|
2007-08-14 06:34:21 +00:00
|
|
|
.long AlignmentException - _start + _START_OFFSET
|
|
|
|
|
.long int_return - _start + _START_OFFSET
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/* Program check exception */
|
|
|
|
|
. = 0x0700
|
|
|
|
|
ProgramCheck:
|
2007-06-22 12:58:04 +00:00
|
|
|
EXCEPTION_PROLOG(SRR0, SRR1)
|
2003-10-15 23:53:47 +00:00
|
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
|
|
|
li r20,MSR_KERNEL
|
|
|
|
|
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
|
|
|
|
|
lwz r6,GOT(transfer_to_handler)
|
|
|
|
|
mtlr r6
|
|
|
|
|
blrl
|
|
|
|
|
.L_ProgramCheck:
|
2007-08-14 06:34:21 +00:00
|
|
|
.long ProgramCheckException - _start + _START_OFFSET
|
|
|
|
|
.long int_return - _start + _START_OFFSET
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/* No FPU on MPC85xx. This exception is not supposed to happen.
|
|
|
|
|
*/
|
|
|
|
|
STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
|
|
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
. = 0x0900
|
2003-10-15 23:53:47 +00:00
|
|
|
/*
|
|
|
|
|
* r0 - SYSCALL number
|
|
|
|
|
* r3-... arguments
|
|
|
|
|
*/
|
|
|
|
|
SystemCall:
|
2007-08-14 06:34:21 +00:00
|
|
|
addis r11,r0,0 /* get functions table addr */
|
|
|
|
|
ori r11,r11,0 /* Note: this code is patched in trap_init */
|
|
|
|
|
addis r12,r0,0 /* get number of functions */
|
2005-05-13 22:49:36 +00:00
|
|
|
ori r12,r12,0
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
cmplw 0,r0,r12
|
2005-05-13 22:49:36 +00:00
|
|
|
bge 1f
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
|
2005-05-13 22:49:36 +00:00
|
|
|
add r11,r11,r0
|
|
|
|
|
lwz r11,0(r11)
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
li r20,0xd00-4 /* Get stack pointer */
|
2005-05-13 22:49:36 +00:00
|
|
|
lwz r12,0(r20)
|
2007-08-14 06:34:21 +00:00
|
|
|
subi r12,r12,12 /* Adjust stack pointer */
|
2005-05-13 22:49:36 +00:00
|
|
|
li r0,0xc00+_end_back-SystemCall
|
2007-08-14 06:34:21 +00:00
|
|
|
cmplw 0,r0,r12 /* Check stack overflow */
|
2005-05-13 22:49:36 +00:00
|
|
|
bgt 1f
|
|
|
|
|
stw r12,0(r20)
|
|
|
|
|
|
|
|
|
|
mflr r0
|
|
|
|
|
stw r0,0(r12)
|
|
|
|
|
mfspr r0,SRR0
|
|
|
|
|
stw r0,4(r12)
|
|
|
|
|
mfspr r0,SRR1
|
|
|
|
|
stw r0,8(r12)
|
|
|
|
|
|
|
|
|
|
li r12,0xc00+_back-SystemCall
|
|
|
|
|
mtlr r12
|
|
|
|
|
mtspr SRR0,r11
|
|
|
|
|
|
|
|
|
|
1: SYNC
|
2003-10-15 23:53:47 +00:00
|
|
|
rfi
|
|
|
|
|
_back:
|
|
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
mfmsr r11 /* Disable interrupts */
|
|
|
|
|
li r12,0
|
|
|
|
|
ori r12,r12,MSR_EE
|
|
|
|
|
andc r11,r11,r12
|
|
|
|
|
SYNC /* Some chip revs need this... */
|
|
|
|
|
mtmsr r11
|
2003-10-15 23:53:47 +00:00
|
|
|
SYNC
|
|
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
li r12,0xd00-4 /* restore regs */
|
|
|
|
|
lwz r12,0(r12)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
lwz r11,0(r12)
|
|
|
|
|
mtlr r11
|
|
|
|
|
lwz r11,4(r12)
|
|
|
|
|
mtspr SRR0,r11
|
|
|
|
|
lwz r11,8(r12)
|
|
|
|
|
mtspr SRR1,r11
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
addi r12,r12,12 /* Adjust stack pointer */
|
|
|
|
|
li r20,0xd00-4
|
|
|
|
|
stw r12,0(r20)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
SYNC
|
|
|
|
|
rfi
|
|
|
|
|
_end_back:
|
|
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
|
|
|
|
|
STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
|
|
|
|
|
STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
|
|
|
|
|
STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
.globl _end_of_vectors
|
2003-10-15 23:53:47 +00:00
|
|
|
_end_of_vectors:
|
|
|
|
|
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
. = . + (0x100 - ( . & 0xff )) /* align for debug */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* This code finishes saving the registers to the exception frame
|
|
|
|
|
* and jumps to the appropriate handler for the exception.
|
|
|
|
|
* Register r21 is pointer into trap frame, r1 has new stack pointer.
|
|
|
|
|
*/
|
|
|
|
|
.globl transfer_to_handler
|
|
|
|
|
transfer_to_handler:
|
|
|
|
|
stw r22,_NIP(r21)
|
|
|
|
|
lis r22,MSR_POW@h
|
|
|
|
|
andc r23,r23,r22
|
|
|
|
|
stw r23,_MSR(r21)
|
|
|
|
|
SAVE_GPR(7, r21)
|
|
|
|
|
SAVE_4GPRS(8, r21)
|
|
|
|
|
SAVE_8GPRS(12, r21)
|
|
|
|
|
SAVE_8GPRS(24, r21)
|
|
|
|
|
|
|
|
|
|
mflr r23
|
|
|
|
|
andi. r24,r23,0x3f00 /* get vector offset */
|
|
|
|
|
stw r24,TRAP(r21)
|
|
|
|
|
li r22,0
|
|
|
|
|
stw r22,RESULT(r21)
|
|
|
|
|
mtspr SPRG2,r22 /* r1 is now kernel sp */
|
|
|
|
|
|
|
|
|
|
lwz r24,0(r23) /* virtual address of handler */
|
|
|
|
|
lwz r23,4(r23) /* where to go when done */
|
|
|
|
|
mtspr SRR0,r24
|
|
|
|
|
mtspr SRR1,r20
|
|
|
|
|
mtlr r23
|
|
|
|
|
SYNC
|
|
|
|
|
rfi /* jump to handler, enable MMU */
|
|
|
|
|
|
|
|
|
|
int_return:
|
|
|
|
|
mfmsr r28 /* Disable interrupts */
|
|
|
|
|
li r4,0
|
|
|
|
|
ori r4,r4,MSR_EE
|
|
|
|
|
andc r28,r28,r4
|
|
|
|
|
SYNC /* Some chip revs need this... */
|
|
|
|
|
mtmsr r28
|
|
|
|
|
SYNC
|
|
|
|
|
lwz r2,_CTR(r1)
|
|
|
|
|
lwz r0,_LINK(r1)
|
|
|
|
|
mtctr r2
|
|
|
|
|
mtlr r0
|
|
|
|
|
lwz r2,_XER(r1)
|
|
|
|
|
lwz r0,_CCR(r1)
|
|
|
|
|
mtspr XER,r2
|
|
|
|
|
mtcrf 0xFF,r0
|
|
|
|
|
REST_10GPRS(3, r1)
|
|
|
|
|
REST_10GPRS(13, r1)
|
|
|
|
|
REST_8GPRS(23, r1)
|
|
|
|
|
REST_GPR(31, r1)
|
|
|
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
|
|
|
lwz r0,_MSR(r1)
|
|
|
|
|
mtspr SRR0,r2
|
|
|
|
|
mtspr SRR1,r0
|
|
|
|
|
lwz r0,GPR0(r1)
|
|
|
|
|
lwz r2,GPR2(r1)
|
|
|
|
|
lwz r1,GPR1(r1)
|
|
|
|
|
SYNC
|
|
|
|
|
rfi
|
|
|
|
|
|
|
|
|
|
crit_return:
|
|
|
|
|
mfmsr r28 /* Disable interrupts */
|
|
|
|
|
li r4,0
|
|
|
|
|
ori r4,r4,MSR_EE
|
|
|
|
|
andc r28,r28,r4
|
|
|
|
|
SYNC /* Some chip revs need this... */
|
|
|
|
|
mtmsr r28
|
|
|
|
|
SYNC
|
|
|
|
|
lwz r2,_CTR(r1)
|
|
|
|
|
lwz r0,_LINK(r1)
|
|
|
|
|
mtctr r2
|
|
|
|
|
mtlr r0
|
|
|
|
|
lwz r2,_XER(r1)
|
|
|
|
|
lwz r0,_CCR(r1)
|
|
|
|
|
mtspr XER,r2
|
|
|
|
|
mtcrf 0xFF,r0
|
|
|
|
|
REST_10GPRS(3, r1)
|
|
|
|
|
REST_10GPRS(13, r1)
|
|
|
|
|
REST_8GPRS(23, r1)
|
|
|
|
|
REST_GPR(31, r1)
|
|
|
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
|
|
|
lwz r0,_MSR(r1)
|
2007-08-14 06:34:21 +00:00
|
|
|
mtspr SPRN_CSRR0,r2
|
|
|
|
|
mtspr SPRN_CSRR1,r0
|
2003-10-15 23:53:47 +00:00
|
|
|
lwz r0,GPR0(r1)
|
|
|
|
|
lwz r2,GPR2(r1)
|
|
|
|
|
lwz r1,GPR1(r1)
|
|
|
|
|
SYNC
|
|
|
|
|
rfci
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
mck_return:
|
|
|
|
|
mfmsr r28 /* Disable interrupts */
|
|
|
|
|
li r4,0
|
|
|
|
|
ori r4,r4,MSR_EE
|
|
|
|
|
andc r28,r28,r4
|
|
|
|
|
SYNC /* Some chip revs need this... */
|
|
|
|
|
mtmsr r28
|
|
|
|
|
SYNC
|
|
|
|
|
lwz r2,_CTR(r1)
|
|
|
|
|
lwz r0,_LINK(r1)
|
|
|
|
|
mtctr r2
|
|
|
|
|
mtlr r0
|
|
|
|
|
lwz r2,_XER(r1)
|
|
|
|
|
lwz r0,_CCR(r1)
|
|
|
|
|
mtspr XER,r2
|
|
|
|
|
mtcrf 0xFF,r0
|
|
|
|
|
REST_10GPRS(3, r1)
|
|
|
|
|
REST_10GPRS(13, r1)
|
|
|
|
|
REST_8GPRS(23, r1)
|
|
|
|
|
REST_GPR(31, r1)
|
|
|
|
|
lwz r2,_NIP(r1) /* Restore environment */
|
|
|
|
|
lwz r0,_MSR(r1)
|
|
|
|
|
mtspr SPRN_MCSRR0,r2
|
|
|
|
|
mtspr SPRN_MCSRR1,r0
|
|
|
|
|
lwz r0,GPR0(r1)
|
|
|
|
|
lwz r2,GPR2(r1)
|
|
|
|
|
lwz r1,GPR1(r1)
|
|
|
|
|
SYNC
|
|
|
|
|
rfmci
|
|
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
/* Cache functions.
|
|
|
|
|
*/
|
2008-09-22 19:11:10 +00:00
|
|
|
.globl invalidate_icache
|
2003-10-15 23:53:47 +00:00
|
|
|
invalidate_icache:
|
|
|
|
|
mfspr r0,L1CSR1
|
2007-08-14 06:34:21 +00:00
|
|
|
ori r0,r0,L1CSR1_ICFI
|
|
|
|
|
msync
|
|
|
|
|
isync
|
2003-10-15 23:53:47 +00:00
|
|
|
mtspr L1CSR1,r0
|
|
|
|
|
isync
|
2007-08-14 06:34:21 +00:00
|
|
|
blr /* entire I cache */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2008-09-22 19:11:10 +00:00
|
|
|
.globl invalidate_dcache
|
2003-10-15 23:53:47 +00:00
|
|
|
invalidate_dcache:
|
|
|
|
|
mfspr r0,L1CSR0
|
2007-08-14 06:34:21 +00:00
|
|
|
ori r0,r0,L1CSR0_DCFI
|
2003-10-15 23:53:47 +00:00
|
|
|
msync
|
|
|
|
|
isync
|
|
|
|
|
mtspr L1CSR0,r0
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl icache_enable
|
|
|
|
|
icache_enable:
|
|
|
|
|
mflr r8
|
|
|
|
|
bl invalidate_icache
|
|
|
|
|
mtlr r8
|
|
|
|
|
isync
|
|
|
|
|
mfspr r4,L1CSR1
|
|
|
|
|
ori r4,r4,0x0001
|
|
|
|
|
oris r4,r4,0x0001
|
|
|
|
|
mtspr L1CSR1,r4
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl icache_disable
|
|
|
|
|
icache_disable:
|
|
|
|
|
mfspr r0,L1CSR1
|
2007-08-14 06:34:21 +00:00
|
|
|
lis r3,0
|
|
|
|
|
ori r3,r3,L1CSR1_ICE
|
|
|
|
|
andc r0,r0,r3
|
2003-10-15 23:53:47 +00:00
|
|
|
mtspr L1CSR1,r0
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl icache_status
|
|
|
|
|
icache_status:
|
|
|
|
|
mfspr r3,L1CSR1
|
2007-08-14 06:34:21 +00:00
|
|
|
andi. r3,r3,L1CSR1_ICE
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl dcache_enable
|
|
|
|
|
dcache_enable:
|
|
|
|
|
mflr r8
|
|
|
|
|
bl invalidate_dcache
|
|
|
|
|
mtlr r8
|
|
|
|
|
isync
|
|
|
|
|
mfspr r0,L1CSR0
|
|
|
|
|
ori r0,r0,0x0001
|
|
|
|
|
oris r0,r0,0x0001
|
|
|
|
|
msync
|
|
|
|
|
isync
|
|
|
|
|
mtspr L1CSR0,r0
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl dcache_disable
|
|
|
|
|
dcache_disable:
|
2007-08-14 06:34:21 +00:00
|
|
|
mfspr r3,L1CSR0
|
|
|
|
|
lis r4,0
|
|
|
|
|
ori r4,r4,L1CSR0_DCE
|
|
|
|
|
andc r3,r3,r4
|
2003-10-15 23:53:47 +00:00
|
|
|
mtspr L1CSR0,r0
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl dcache_status
|
|
|
|
|
dcache_status:
|
|
|
|
|
mfspr r3,L1CSR0
|
2007-08-14 06:34:21 +00:00
|
|
|
andi. r3,r3,L1CSR0_DCE
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl get_pir
|
|
|
|
|
get_pir:
|
2007-08-14 06:34:21 +00:00
|
|
|
mfspr r3,PIR
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl get_pvr
|
|
|
|
|
get_pvr:
|
2007-08-14 06:34:21 +00:00
|
|
|
mfspr r3,PVR
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
2004-06-09 00:34:46 +00:00
|
|
|
.globl get_svr
|
|
|
|
|
get_svr:
|
2007-08-14 06:34:21 +00:00
|
|
|
mfspr r3,SVR
|
2004-06-09 00:34:46 +00:00
|
|
|
blr
|
|
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
.globl wr_tcr
|
|
|
|
|
wr_tcr:
|
2007-08-14 06:34:21 +00:00
|
|
|
mtspr TCR,r3
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: in8 */
|
|
|
|
|
/* Description: Input 8 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl in8
|
|
|
|
|
in8:
|
|
|
|
|
lbz r3,0x0000(r3)
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: out8 */
|
|
|
|
|
/* Description: Output 8 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl out8
|
|
|
|
|
out8:
|
|
|
|
|
stb r4,0x0000(r3)
|
2007-09-26 21:35:54 +00:00
|
|
|
sync
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: out16 */
|
|
|
|
|
/* Description: Output 16 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl out16
|
|
|
|
|
out16:
|
|
|
|
|
sth r4,0x0000(r3)
|
2007-09-26 21:35:54 +00:00
|
|
|
sync
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: out16r */
|
|
|
|
|
/* Description: Byte reverse and output 16 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl out16r
|
|
|
|
|
out16r:
|
|
|
|
|
sthbrx r4,r0,r3
|
2007-09-26 21:35:54 +00:00
|
|
|
sync
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: out32 */
|
|
|
|
|
/* Description: Output 32 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl out32
|
|
|
|
|
out32:
|
|
|
|
|
stw r4,0x0000(r3)
|
2007-09-26 21:35:54 +00:00
|
|
|
sync
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: out32r */
|
|
|
|
|
/* Description: Byte reverse and output 32 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl out32r
|
|
|
|
|
out32r:
|
|
|
|
|
stwbrx r4,r0,r3
|
2007-09-26 21:35:54 +00:00
|
|
|
sync
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: in16 */
|
|
|
|
|
/* Description: Input 16 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl in16
|
|
|
|
|
in16:
|
|
|
|
|
lhz r3,0x0000(r3)
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: in16r */
|
|
|
|
|
/* Description: Input 16 bits and byte reverse */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl in16r
|
|
|
|
|
in16r:
|
|
|
|
|
lhbrx r3,r0,r3
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: in32 */
|
|
|
|
|
/* Description: Input 32 bits */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl in32
|
|
|
|
|
in32:
|
|
|
|
|
lwz 3,0x0000(3)
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
/* Function: in32r */
|
|
|
|
|
/* Description: Input 32 bits and byte reverse */
|
|
|
|
|
/*------------------------------------------------------------------------------- */
|
|
|
|
|
.globl in32r
|
|
|
|
|
in32r:
|
|
|
|
|
lwbrx r3,r0,r3
|
|
|
|
|
blr
|
ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
|
|
|
#endif /* !CONFIG_NAND_SPL */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/*------------------------------------------------------------------------------*/
|
|
|
|
|
|
2009-09-11 16:27:00 +00:00
|
|
|
/*
|
|
|
|
|
* void write_tlb(mas0, mas1, mas2, mas3, mas7)
|
|
|
|
|
*/
|
|
|
|
|
.globl write_tlb
|
|
|
|
|
write_tlb:
|
|
|
|
|
mtspr MAS0,r3
|
|
|
|
|
mtspr MAS1,r4
|
|
|
|
|
mtspr MAS2,r5
|
|
|
|
|
mtspr MAS3,r6
|
|
|
|
|
#ifdef CONFIG_ENABLE_36BIT_PHYS
|
|
|
|
|
mtspr MAS7,r7
|
|
|
|
|
#endif
|
|
|
|
|
li r3,0
|
|
|
|
|
#ifdef CONFIG_SYS_BOOK3E_HV
|
|
|
|
|
mtspr MAS8,r3
|
|
|
|
|
#endif
|
|
|
|
|
isync
|
|
|
|
|
tlbwe
|
|
|
|
|
msync
|
|
|
|
|
isync
|
|
|
|
|
blr
|
|
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
/*
|
|
|
|
|
* void relocate_code (addr_sp, gd, addr_moni)
|
|
|
|
|
*
|
|
|
|
|
* This "function" does not return, instead it continues in RAM
|
|
|
|
|
* after relocating the monitor code.
|
|
|
|
|
*
|
|
|
|
|
* r3 = dest
|
|
|
|
|
* r4 = src
|
|
|
|
|
* r5 = length in bytes
|
|
|
|
|
* r6 = cachelinesize
|
|
|
|
|
*/
|
|
|
|
|
.globl relocate_code
|
|
|
|
|
relocate_code:
|
2007-08-14 06:34:21 +00:00
|
|
|
mr r1,r3 /* Set new stack pointer */
|
|
|
|
|
mr r9,r4 /* Save copy of Init Data pointer */
|
|
|
|
|
mr r10,r5 /* Save copy of Destination Address */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
mr r3,r5 /* Destination Address */
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
|
|
|
|
|
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
|
2003-10-15 23:53:47 +00:00
|
|
|
lwz r5,GOT(__init_end)
|
|
|
|
|
sub r5,r5,r4
|
2008-10-16 13:01:15 +00:00
|
|
|
li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Fix GOT pointer:
|
|
|
|
|
*
|
2008-10-16 13:01:15 +00:00
|
|
|
* New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
|
2003-10-15 23:53:47 +00:00
|
|
|
*
|
|
|
|
|
* Offset:
|
|
|
|
|
*/
|
2007-08-14 06:34:21 +00:00
|
|
|
sub r15,r10,r4
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/* First our own GOT */
|
2007-08-14 06:34:21 +00:00
|
|
|
add r14,r14,r15
|
2003-10-15 23:53:47 +00:00
|
|
|
/* the the one used by the C code */
|
2007-08-14 06:34:21 +00:00
|
|
|
add r30,r30,r15
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now relocate code
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
cmplw cr1,r3,r4
|
|
|
|
|
addi r0,r5,3
|
|
|
|
|
srwi. r0,r0,2
|
|
|
|
|
beq cr1,4f /* In place copy is not necessary */
|
|
|
|
|
beq 7f /* Protect against 0 count */
|
|
|
|
|
mtctr r0
|
|
|
|
|
bge cr1,2f
|
|
|
|
|
|
|
|
|
|
la r8,-4(r4)
|
|
|
|
|
la r7,-4(r3)
|
|
|
|
|
1: lwzu r0,4(r8)
|
|
|
|
|
stwu r0,4(r7)
|
|
|
|
|
bdnz 1b
|
|
|
|
|
b 4f
|
|
|
|
|
|
|
|
|
|
2: slwi r0,r0,2
|
|
|
|
|
add r8,r4,r0
|
|
|
|
|
add r7,r3,r0
|
|
|
|
|
3: lwzu r0,-4(r8)
|
|
|
|
|
stwu r0,-4(r7)
|
|
|
|
|
bdnz 3b
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now flush the cache: note that we must start from a cache aligned
|
|
|
|
|
* address. Otherwise we might miss one cache line.
|
|
|
|
|
*/
|
|
|
|
|
4: cmpwi r6,0
|
|
|
|
|
add r5,r3,r5
|
|
|
|
|
beq 7f /* Always flush prefetch queue in any case */
|
|
|
|
|
subi r0,r6,1
|
|
|
|
|
andc r3,r3,r0
|
|
|
|
|
mr r4,r3
|
|
|
|
|
5: dcbst 0,r4
|
|
|
|
|
add r4,r4,r6
|
|
|
|
|
cmplw r4,r5
|
|
|
|
|
blt 5b
|
|
|
|
|
sync /* Wait for all dcbst to complete on bus */
|
|
|
|
|
mr r4,r3
|
|
|
|
|
6: icbi 0,r4
|
|
|
|
|
add r4,r4,r6
|
|
|
|
|
cmplw r4,r5
|
|
|
|
|
blt 6b
|
|
|
|
|
7: sync /* Wait for all icbi to complete on bus */
|
|
|
|
|
isync
|
|
|
|
|
|
2005-10-04 22:00:54 +00:00
|
|
|
/*
|
|
|
|
|
* Re-point the IVPR at RAM
|
|
|
|
|
*/
|
|
|
|
|
mtspr IVPR,r10
|
2005-10-04 22:19:34 +00:00
|
|
|
|
2003-10-15 23:53:47 +00:00
|
|
|
/*
|
|
|
|
|
* We are done. Do not return, instead branch to second part of board
|
|
|
|
|
* initialization, now running from RAM.
|
|
|
|
|
*/
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
addi r0,r10,in_ram - _start + _START_OFFSET
|
2003-10-15 23:53:47 +00:00
|
|
|
mtlr r0
|
|
|
|
|
blr /* NEVER RETURNS! */
|
2007-08-14 06:34:21 +00:00
|
|
|
.globl in_ram
|
2003-10-15 23:53:47 +00:00
|
|
|
in_ram:
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Relocation Function, r14 point to got2+0x8000
|
|
|
|
|
*
|
|
|
|
|
* Adjust got2 pointers, no need to check for 0, this code
|
|
|
|
|
* already puts a few entries in the table.
|
|
|
|
|
*/
|
|
|
|
|
li r0,__got2_entries@sectoff@l
|
|
|
|
|
la r3,GOT(_GOT2_TABLE_)
|
|
|
|
|
lwz r11,GOT(_GOT2_TABLE_)
|
|
|
|
|
mtctr r0
|
|
|
|
|
sub r11,r3,r11
|
|
|
|
|
addi r3,r3,-4
|
|
|
|
|
1: lwzu r0,4(r3)
|
2009-10-08 00:03:51 +00:00
|
|
|
cmpwi r0,0
|
|
|
|
|
beq- 2f
|
2003-10-15 23:53:47 +00:00
|
|
|
add r0,r0,r11
|
|
|
|
|
stw r0,0(r3)
|
2009-10-08 00:03:51 +00:00
|
|
|
2: bdnz 1b
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Now adjust the fixups and the pointers to the fixups
|
|
|
|
|
* in case we need to move ourselves again.
|
|
|
|
|
*/
|
2009-10-08 00:03:51 +00:00
|
|
|
li r0,__fixup_entries@sectoff@l
|
2003-10-15 23:53:47 +00:00
|
|
|
lwz r3,GOT(_FIXUP_TABLE_)
|
|
|
|
|
cmpwi r0,0
|
|
|
|
|
mtctr r0
|
|
|
|
|
addi r3,r3,-4
|
|
|
|
|
beq 4f
|
|
|
|
|
3: lwzu r4,4(r3)
|
|
|
|
|
lwzux r0,r4,r11
|
|
|
|
|
add r0,r0,r11
|
|
|
|
|
stw r10,0(r3)
|
|
|
|
|
stw r0,0(r4)
|
|
|
|
|
bdnz 3b
|
|
|
|
|
4:
|
|
|
|
|
clear_bss:
|
|
|
|
|
/*
|
|
|
|
|
* Now clear BSS segment
|
|
|
|
|
*/
|
|
|
|
|
lwz r3,GOT(__bss_start)
|
|
|
|
|
lwz r4,GOT(_end)
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
cmplw 0,r3,r4
|
2003-10-15 23:53:47 +00:00
|
|
|
beq 6f
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
li r0,0
|
2003-10-15 23:53:47 +00:00
|
|
|
5:
|
2007-08-14 06:34:21 +00:00
|
|
|
stw r0,0(r3)
|
|
|
|
|
addi r3,r3,4
|
|
|
|
|
cmplw 0,r3,r4
|
2003-10-15 23:53:47 +00:00
|
|
|
bne 5b
|
|
|
|
|
6:
|
|
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
mr r3,r9 /* Init Data pointer */
|
|
|
|
|
mr r4,r10 /* Destination Address */
|
2003-10-15 23:53:47 +00:00
|
|
|
bl board_init_r
|
|
|
|
|
|
ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
|
|
|
#ifndef CONFIG_NAND_SPL
|
2003-10-15 23:53:47 +00:00
|
|
|
/*
|
|
|
|
|
* Copy exception vector code to low memory
|
|
|
|
|
*
|
|
|
|
|
* r3: dest_addr
|
|
|
|
|
* r7: source address, r8: end address, r9: target address
|
|
|
|
|
*/
|
2005-05-13 22:49:36 +00:00
|
|
|
.globl trap_init
|
2003-10-15 23:53:47 +00:00
|
|
|
trap_init:
|
2007-08-14 06:34:21 +00:00
|
|
|
lwz r7,GOT(_start_of_vectors)
|
|
|
|
|
lwz r8,GOT(_end_of_vectors)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
li r9,0x100 /* reset vector always at 0x100 */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
cmplw 0,r7,r8
|
2005-05-13 22:49:36 +00:00
|
|
|
bgelr /* return if r7>=r8 - just in case */
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
mflr r4 /* save link register */
|
2003-10-15 23:53:47 +00:00
|
|
|
1:
|
2007-08-14 06:34:21 +00:00
|
|
|
lwz r0,0(r7)
|
|
|
|
|
stw r0,0(r9)
|
|
|
|
|
addi r7,r7,4
|
|
|
|
|
addi r9,r9,4
|
|
|
|
|
cmplw 0,r7,r8
|
2005-05-13 22:49:36 +00:00
|
|
|
bne 1b
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* relocate `hdlr' and `int_return' entries
|
|
|
|
|
*/
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_CriticalInput - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_MachineCheck - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_DataStorage - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_InstStorage - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_ExtInterrupt - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_Alignment - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_ProgramCheck - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_FPUnavailable - _start + _START_OFFSET
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
li r7,.L_Decrementer - _start + _START_OFFSET
|
|
|
|
|
bl trap_reloc
|
|
|
|
|
li r7,.L_IntervalTimer - _start + _START_OFFSET
|
|
|
|
|
li r8,_end_of_vectors - _start + _START_OFFSET
|
2003-10-15 23:53:47 +00:00
|
|
|
2:
|
2005-05-13 22:49:36 +00:00
|
|
|
bl trap_reloc
|
2007-08-14 06:34:21 +00:00
|
|
|
addi r7,r7,0x100 /* next exception vector */
|
|
|
|
|
cmplw 0,r7,r8
|
2005-05-13 22:49:36 +00:00
|
|
|
blt 2b
|
|
|
|
|
|
|
|
|
|
lis r7,0x0
|
2007-08-14 06:34:21 +00:00
|
|
|
mtspr IVPR,r7
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2005-05-13 22:49:36 +00:00
|
|
|
mtlr r4 /* restore link register */
|
2003-10-15 23:53:47 +00:00
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Function: relocate entries for one exception vector
|
|
|
|
|
*/
|
|
|
|
|
trap_reloc:
|
2007-08-14 06:34:21 +00:00
|
|
|
lwz r0,0(r7) /* hdlr ... */
|
|
|
|
|
add r0,r0,r3 /* ... += dest_addr */
|
|
|
|
|
stw r0,0(r7)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
2007-08-14 06:34:21 +00:00
|
|
|
lwz r0,4(r7) /* int_return ... */
|
|
|
|
|
add r0,r0,r3 /* ... += dest_addr */
|
|
|
|
|
stw r0,4(r7)
|
2003-10-15 23:53:47 +00:00
|
|
|
|
|
|
|
|
blr
|
|
|
|
|
|
|
|
|
|
.globl unlock_ram_in_cache
|
|
|
|
|
unlock_ram_in_cache:
|
|
|
|
|
/* invalidate the INIT_RAM section */
|
2008-10-23 06:47:37 +00:00
|
|
|
lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
|
|
|
|
|
ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
|
2008-01-08 07:22:21 +00:00
|
|
|
mfspr r4,L1CFG0
|
|
|
|
|
andi. r4,r4,0x1ff
|
|
|
|
|
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
|
2007-08-14 06:34:21 +00:00
|
|
|
mtctr r4
|
2008-02-27 22:30:47 +00:00
|
|
|
1: dcbi r0,r3
|
2008-10-16 13:01:15 +00:00
|
|
|
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
|
2003-10-15 23:53:47 +00:00
|
|
|
bdnz 1b
|
2008-02-27 22:30:47 +00:00
|
|
|
sync
|
2008-02-27 20:29:58 +00:00
|
|
|
|
|
|
|
|
/* Invalidate the TLB entries for the cache */
|
2008-10-16 13:01:15 +00:00
|
|
|
lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
|
|
|
|
|
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
|
2008-02-27 20:29:58 +00:00
|
|
|
tlbivax 0,r3
|
|
|
|
|
addi r3,r3,0x1000
|
|
|
|
|
tlbivax 0,r3
|
|
|
|
|
addi r3,r3,0x1000
|
|
|
|
|
tlbivax 0,r3
|
|
|
|
|
addi r3,r3,0x1000
|
|
|
|
|
tlbivax 0,r3
|
2003-10-15 23:53:47 +00:00
|
|
|
isync
|
|
|
|
|
blr
|
2008-09-22 19:11:10 +00:00
|
|
|
|
|
|
|
|
.globl flush_dcache
|
|
|
|
|
flush_dcache:
|
|
|
|
|
mfspr r3,SPRN_L1CFG0
|
|
|
|
|
|
|
|
|
|
rlwinm r5,r3,9,3 /* Extract cache block size */
|
|
|
|
|
twlgti r5,1 /* Only 32 and 64 byte cache blocks
|
|
|
|
|
* are currently defined.
|
|
|
|
|
*/
|
|
|
|
|
li r4,32
|
|
|
|
|
subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
|
|
|
|
|
* log2(number of ways)
|
|
|
|
|
*/
|
|
|
|
|
slw r5,r4,r5 /* r5 = cache block size */
|
|
|
|
|
|
|
|
|
|
rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
|
|
|
|
|
mulli r7,r7,13 /* An 8-way cache will require 13
|
|
|
|
|
* loads per set.
|
|
|
|
|
*/
|
|
|
|
|
slw r7,r7,r6
|
|
|
|
|
|
|
|
|
|
/* save off HID0 and set DCFA */
|
|
|
|
|
mfspr r8,SPRN_HID0
|
|
|
|
|
ori r9,r8,HID0_DCFA@l
|
|
|
|
|
mtspr SPRN_HID0,r9
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
lis r4,0
|
|
|
|
|
mtctr r7
|
|
|
|
|
|
|
|
|
|
1: lwz r3,0(r4) /* Load... */
|
|
|
|
|
add r4,r4,r5
|
|
|
|
|
bdnz 1b
|
|
|
|
|
|
|
|
|
|
msync
|
|
|
|
|
lis r4,0
|
|
|
|
|
mtctr r7
|
|
|
|
|
|
|
|
|
|
1: dcbf 0,r4 /* ...and flush. */
|
|
|
|
|
add r4,r4,r5
|
|
|
|
|
bdnz 1b
|
|
|
|
|
|
|
|
|
|
/* restore HID0 */
|
|
|
|
|
mtspr SPRN_HID0,r8
|
|
|
|
|
isync
|
|
|
|
|
|
|
|
|
|
blr
|
2009-08-14 18:37:54 +00:00
|
|
|
|
|
|
|
|
.globl setup_ivors
|
|
|
|
|
setup_ivors:
|
|
|
|
|
|
|
|
|
|
#include "fixed_ivor.S"
|
|
|
|
|
blr
|
ppc/85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NAND loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-11 06:19:10 +00:00
|
|
|
#endif /* !CONFIG_NAND_SPL */
|
