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85xx: Add support for additional e500mc features

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* Enable backside L2
* e500mc no longer has timebase enable in HID (moved to CCSR register)

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-03-19 09:16:10 -05:00
parent c360ceac02
commit 1b3e4044a2
4 changed files with 94 additions and 1 deletions
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13
cpu/mpc85xx/cpu_init.c
View file

@ -345,6 +345,19 @@ int cpu_init_r(void)
asm("msync;isync");
puts("enabled\n");
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
/* invalidate the L2 cache */
mtspr(SPRN_L2CSR0, L2CSR0_L2FI);
while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI)
;
/* enable the cache */
mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E)
printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
#else
puts("disabled\n");
#endif

64
cpu/mpc85xx/fdt.c
View file

@ -80,7 +80,9 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
}
#endif
#ifdef CONFIG_L2_CACHE
#define ft_fixup_l3cache(x, y)
#if defined(CONFIG_L2_CACHE)
/* return size in kilobytes */
static inline u32 l2cache_size(void)
{
@ -157,6 +159,66 @@ static inline void ft_fixup_l2cache(void *blob)
fdt_setprop_cell(blob, off, "cache-sets", num_sets);
fdt_setprop_cell(blob, off, "cache-level", 2);
fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
/* we dont bother w/L3 since no platform of this type has one */
}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
static inline void ft_fixup_l2cache(void *blob)
{
int off, l2_off, l3_off = -1;
u32 *ph;
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
u32 size, line_size, num_ways, num_sets;
size = (l2cfg0 & 0x3fff) * 64 * 1024;
num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
num_sets = size / (line_size * num_ways);
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
if (ph == NULL) {
debug("no next-level-cache property\n");
goto next;
}
l2_off = fdt_node_offset_by_phandle(blob, *ph);
if (l2_off < 0) {
printf("%s: %s\n", __func__, fdt_strerror(off));
goto next;
}
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
fdt_setprop_cell(blob, l2_off, "cache-size", size);
fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
fdt_setprop_cell(blob, l2_off, "cache-level", 2);
fdt_setprop(blob, l2_off, "compatible", "cache", 6);
if (l3_off < 0) {
ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
if (ph == NULL) {
debug("no next-level-cache property\n");
goto next;
}
l3_off = *ph;
}
next:
off = fdt_node_offset_by_prop_value(blob, off,
"device_type", "cpu", 4);
}
if (l3_off > 0) {
l3_off = fdt_node_offset_by_phandle(blob, l3_off);
if (l3_off < 0) {
printf("%s: %s\n", __func__, fdt_strerror(off));
return ;
}
ft_fixup_l3cache(blob, l3_off);
}
}
#else
#define ft_fixup_l2cache(x)

16
cpu/mpc85xx/release.S
View file

@ -76,6 +76,22 @@ __secondary_start_page:
slwi r8,r4,5
add r10,r3,r8
#ifdef CONFIG_BACKSIDE_L2_CACHE
/* Enable/invalidate the L2 cache */
msync
lis r3,L2CSR0_L2FI@h
mtspr SPRN_L2CSR0,r3
1:
mfspr r3,SPRN_L2CSR0
andis. r1,r3,L2CSR0_L2FI@h
bne 1b
lis r3,CONFIG_SYS_INIT_L2CSR0@h
ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
mtspr SPRN_L2CSR0,r3
isync
#endif
#define EPAPR_MAGIC (0x45504150)
#define ENTRY_ADDR_UPPER 0
#define ENTRY_ADDR_LOWER 4

2
cpu/mpc85xx/start.S
View file

@ -161,7 +161,9 @@ _start_e500:
#if defined(CONFIG_ENABLE_36BIT_PHYS)
ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
#endif
#ifndef CONFIG_E500MC
ori r0,r0,HID0_TBEN@l /* Enable Timebase */
#endif
mtspr HID0,r0
#ifndef CONFIG_E500MC