2023-04-12 07:38:28 +00:00
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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/*
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2023-04-12 07:38:28 +00:00
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* Device Tree Include file for NXP Layerscape-1088A family SoC.
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*
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* Copyright 2017-2020 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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*
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*/
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2023-03-15 11:04:11 +00:00
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#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
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2021-02-05 11:01:53 +00:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2023-04-12 07:38:28 +00:00
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#include <dt-bindings/thermal/thermal.h>
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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/ {
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compatible = "fsl,ls1088a";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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2023-04-12 07:38:28 +00:00
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aliases {
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crypto = &crypto;
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rtc1 = &ftm_alarm0;
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};
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2023-04-12 07:38:21 +00:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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/* We have 2 clusters having 4 Cortex-A53 cores each */
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x2>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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clocks = <&clockgen QORIQ_CLK_CMUX 0>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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clocks = <&clockgen QORIQ_CLK_CMUX 1>;
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cpu-idle-states = <&CPU_PH20>;
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#cooling-cells = <2>;
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};
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CPU_PH20: cpu-ph20 {
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compatible = "arm,idle-state";
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idle-state-name = "PH20";
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arm,psci-suspend-param = <0x0>;
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entry-latency-us = <1000>;
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exit-latency-us = <1000>;
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min-residency-us = <3000>;
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};
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};
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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gic: interrupt-controller@6000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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2023-04-12 07:38:18 +00:00
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reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
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<0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
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<0x0 0x0c0c0000 0 0x2000>, /* GICC */
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<0x0 0x0c0d0000 0 0x1000>, /* GICH */
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<0x0 0x0c0e0000 0 0x20000>; /* GICV */
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interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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its: gic-its@6020000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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reg = <0x0 0x6020000 0 0x20000>;
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};
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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};
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2023-04-12 07:38:28 +00:00
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thermal-zones {
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core-cluster {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 0>;
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trips {
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core_cluster_alert: core-cluster-alert {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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core-cluster-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&core_cluster_alert>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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soc {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&tmu 1>;
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trips {
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soc-crit {
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temperature = <95000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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timer {
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compatible = "arm,armv8-timer";
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2023-04-12 07:38:28 +00:00
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interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
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<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
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<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
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<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
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};
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pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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};
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2023-03-15 11:04:11 +00:00
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sysclk: sysclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "sysclk";
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};
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2023-04-12 07:38:28 +00:00
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reboot {
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compatible = "syscon-reboot";
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regmap = <&reset>;
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offset = <0x0>;
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mask = <0x02>;
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};
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2023-03-15 11:04:09 +00:00
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
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2023-03-15 11:04:11 +00:00
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clockgen: clocking@1300000 {
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compatible = "fsl,ls1088a-clockgen";
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reg = <0 0x1300000 0 0xa0000>;
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#clock-cells = <2>;
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clocks = <&sysclk>;
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};
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2023-04-12 07:38:28 +00:00
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dcfg: dcfg@1e00000 {
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compatible = "fsl,ls1088a-dcfg", "syscon";
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reg = <0x0 0x1e00000 0x0 0x10000>;
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little-endian;
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};
|
|
|
|
|
|
|
|
|
|
reset: syscon@1e60000 {
|
|
|
|
|
compatible = "fsl,ls1088a-reset", "syscon";
|
|
|
|
|
reg = <0x0 0x1e60000 0x0 0x10000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
isc: syscon@1f70000 {
|
|
|
|
|
compatible = "fsl,ls1088a-isc", "syscon";
|
|
|
|
|
reg = <0x0 0x1f70000 0x0 0x10000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x0 0x1f70000 0x10000>;
|
|
|
|
|
|
|
|
|
|
extirq: interrupt-controller@14 {
|
|
|
|
|
compatible = "fsl,ls1088a-extirq";
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
#address-cells = <0>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
reg = <0x14 4>;
|
|
|
|
|
interrupt-map =
|
|
|
|
|
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
interrupt-map-mask = <0xf 0x0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sfp: efuse@1e80000 {
|
|
|
|
|
compatible = "fsl,ls1028a-sfp";
|
|
|
|
|
reg = <0x0 0x1e80000 0x0 0x10000>;
|
2023-03-15 11:04:11 +00:00
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
2023-04-12 07:38:28 +00:00
|
|
|
clock-names = "sfp";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
tmu: tmu@1f80000 {
|
|
|
|
|
compatible = "fsl,qoriq-tmu";
|
|
|
|
|
reg = <0x0 0x1f80000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 23 0x4>;
|
|
|
|
|
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
|
|
|
|
|
fsl,tmu-calibration =
|
|
|
|
|
/* Calibration data group 1 */
|
|
|
|
|
<0x00000000 0x00000023
|
|
|
|
|
0x00000001 0x0000002a
|
|
|
|
|
0x00000002 0x00000030
|
|
|
|
|
0x00000003 0x00000037
|
|
|
|
|
0x00000004 0x0000003d
|
|
|
|
|
0x00000005 0x00000044
|
|
|
|
|
0x00000006 0x0000004a
|
|
|
|
|
0x00000007 0x00000051
|
|
|
|
|
0x00000008 0x00000057
|
|
|
|
|
0x00000009 0x0000005e
|
|
|
|
|
0x0000000a 0x00000064
|
|
|
|
|
0x0000000b 0x0000006b
|
|
|
|
|
/* Calibration data group 2 */
|
|
|
|
|
0x00010000 0x00000022
|
|
|
|
|
0x00010001 0x0000002a
|
|
|
|
|
0x00010002 0x00000032
|
|
|
|
|
0x00010003 0x0000003a
|
|
|
|
|
0x00010004 0x00000042
|
|
|
|
|
0x00010005 0x0000004a
|
|
|
|
|
0x00010006 0x00000052
|
|
|
|
|
0x00010007 0x0000005a
|
|
|
|
|
0x00010008 0x00000062
|
|
|
|
|
0x00010009 0x0000006a
|
|
|
|
|
/* Calibration data group 3 */
|
|
|
|
|
0x00020000 0x00000021
|
|
|
|
|
0x00020001 0x0000002b
|
|
|
|
|
0x00020002 0x00000035
|
|
|
|
|
0x00020003 0x00000040
|
|
|
|
|
0x00020004 0x0000004a
|
|
|
|
|
0x00020005 0x00000054
|
|
|
|
|
0x00020006 0x0000005e
|
|
|
|
|
/* Calibration data group 4 */
|
|
|
|
|
0x00030000 0x00000010
|
|
|
|
|
0x00030001 0x0000001c
|
|
|
|
|
0x00030002 0x00000027
|
|
|
|
|
0x00030003 0x00000032
|
|
|
|
|
0x00030004 0x0000003e
|
|
|
|
|
0x00030005 0x00000049
|
|
|
|
|
0x00030006 0x00000054
|
|
|
|
|
0x00030007 0x00000060>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#thermal-sensor-cells = <1>;
|
2023-03-15 11:04:10 +00:00
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:27 +00:00
|
|
|
dspi: spi@2100000 {
|
|
|
|
|
compatible = "fsl,ls1088a-dspi",
|
|
|
|
|
"fsl,ls1021a-v1.0-dspi";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x0 0x2100000 0x0 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-names = "dspi";
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(2)>;
|
|
|
|
|
spi-num-chipselects = <6>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:28 +00:00
|
|
|
duart0: serial@21c0500 {
|
|
|
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
|
|
|
reg = <0x0 0x21c0500 0x0 0x100>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
|
|
|
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-03-15 11:04:11 +00:00
|
|
|
duart1: serial@21c0600 {
|
2023-03-15 11:04:10 +00:00
|
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
|
|
|
reg = <0x0 0x21c0600 0x0 0x100>;
|
2023-03-15 11:04:11 +00:00
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
|
|
|
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
status = "disabled";
|
2023-03-15 11:04:10 +00:00
|
|
|
};
|
2023-04-12 07:38:18 +00:00
|
|
|
|
2023-04-12 07:38:22 +00:00
|
|
|
gpio0: gpio@2300000 {
|
|
|
|
|
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
|
|
|
|
|
reg = <0x0 0x2300000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
little-endian;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio1: gpio@2310000 {
|
|
|
|
|
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
|
|
|
|
|
reg = <0x0 0x2310000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
little-endian;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio2: gpio@2320000 {
|
|
|
|
|
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
|
|
|
|
|
reg = <0x0 0x2320000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
little-endian;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3: gpio@2330000 {
|
|
|
|
|
compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
|
|
|
|
|
reg = <0x0 0x2330000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
little-endian;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:27 +00:00
|
|
|
ifc: memory-controller@2240000 {
|
|
|
|
|
compatible = "fsl,ifc";
|
|
|
|
|
reg = <0x0 0x2240000 0x0 0x20000>;
|
|
|
|
|
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:23 +00:00
|
|
|
i2c0: i2c@2000000 {
|
|
|
|
|
compatible = "fsl,vf610-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(8)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c1: i2c@2010000 {
|
|
|
|
|
compatible = "fsl,vf610-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x0 0x2010000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(8)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@2020000 {
|
|
|
|
|
compatible = "fsl,vf610-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x0 0x2020000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(8)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@2030000 {
|
|
|
|
|
compatible = "fsl,vf610-i2c";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x0 0x2030000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(8)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:27 +00:00
|
|
|
qspi: spi@20c0000 {
|
|
|
|
|
compatible = "fsl,ls2080a-qspi";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
|
|
|
<0x0 0x20000000 0x0 0x10000000>;
|
|
|
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
|
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clock-names = "qspi_en", "qspi";
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
esdhc: esdhc@2140000 {
|
|
|
|
|
compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
|
|
|
|
|
reg = <0x0 0x2140000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 28 0x4>; /* Level high type */
|
|
|
|
|
clock-frequency = <0>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
|
|
|
|
|
voltage-ranges = <1800 1800 3300 3300>;
|
|
|
|
|
sdhci,auto-cmd12;
|
|
|
|
|
little-endian;
|
|
|
|
|
bus-width = <4>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:24 +00:00
|
|
|
usb0: usb@3100000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
|
|
|
snps,dis_rxdet_inp3_quirk;
|
|
|
|
|
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb1: usb@3110000 {
|
|
|
|
|
compatible = "snps,dwc3";
|
|
|
|
|
reg = <0x0 0x3110000 0x0 0x10000>;
|
|
|
|
|
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dr_mode = "host";
|
|
|
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
|
|
|
snps,dis_rxdet_inp3_quirk;
|
|
|
|
|
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:27 +00:00
|
|
|
sata: sata@3200000 {
|
|
|
|
|
compatible = "fsl,ls1088a-ahci";
|
|
|
|
|
reg = <0x0 0x3200000 0x0 0x10000>,
|
|
|
|
|
<0x7 0x100520 0x0 0x4>;
|
|
|
|
|
reg-names = "ahci", "sata-ecc";
|
|
|
|
|
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
crypto: crypto@8000000 {
|
|
|
|
|
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
|
|
|
|
fsl,sec-era = <8>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges = <0x0 0x00 0x8000000 0x100000>;
|
|
|
|
|
reg = <0x00 0x8000000 0x0 0x100000>;
|
|
|
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
|
|
|
|
|
sec_jr0: jr@10000 {
|
|
|
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
|
|
|
"fsl,sec-v4.0-job-ring";
|
|
|
|
|
reg = <0x10000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sec_jr1: jr@20000 {
|
|
|
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
|
|
|
"fsl,sec-v4.0-job-ring";
|
|
|
|
|
reg = <0x20000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sec_jr2: jr@30000 {
|
|
|
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
|
|
|
"fsl,sec-v4.0-job-ring";
|
|
|
|
|
reg = <0x30000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sec_jr3: jr@40000 {
|
|
|
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
|
|
|
"fsl,sec-v4.0-job-ring";
|
|
|
|
|
reg = <0x40000 0x10000>;
|
|
|
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:19 +00:00
|
|
|
pcie1: pcie@3400000 {
|
|
|
|
|
compatible = "fsl,ls1088a-pcie";
|
|
|
|
|
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
|
|
|
|
|
<0x20 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
|
|
|
reg-names = "regs", "config";
|
|
|
|
|
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
|
|
|
|
interrupt-names = "aer";
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
dma-coherent;
|
|
|
|
|
num-viewport = <256>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
|
|
|
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
|
|
|
msi-parent = <&its>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
|
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
2023-04-12 07:38:20 +00:00
|
|
|
status = "disabled";
|
2023-04-12 07:38:19 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie_ep1: pcie-ep@3400000 {
|
|
|
|
|
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
|
|
|
|
|
reg = <0x00 0x03400000 0x0 0x00100000>,
|
|
|
|
|
<0x20 0x00000000 0x8 0x00000000>;
|
|
|
|
|
reg-names = "regs", "addr_space";
|
|
|
|
|
num-ib-windows = <24>;
|
|
|
|
|
num-ob-windows = <256>;
|
|
|
|
|
max-functions = /bits/ 8 <2>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie2: pcie@3500000 {
|
|
|
|
|
compatible = "fsl,ls1088a-pcie";
|
|
|
|
|
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
|
|
|
|
|
<0x28 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
|
|
|
reg-names = "regs", "config";
|
|
|
|
|
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
|
|
|
|
interrupt-names = "aer";
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
dma-coherent;
|
|
|
|
|
num-viewport = <6>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
|
|
|
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
|
|
|
msi-parent = <&its>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
|
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
2023-04-12 07:38:20 +00:00
|
|
|
status = "disabled";
|
2023-04-12 07:38:19 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie_ep2: pcie-ep@3500000 {
|
|
|
|
|
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
|
|
|
|
|
reg = <0x00 0x03500000 0x0 0x00100000>,
|
|
|
|
|
<0x28 0x00000000 0x8 0x00000000>;
|
|
|
|
|
reg-names = "regs", "addr_space";
|
|
|
|
|
num-ib-windows = <6>;
|
|
|
|
|
num-ob-windows = <6>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie3: pcie@3600000 {
|
|
|
|
|
compatible = "fsl,ls1088a-pcie";
|
|
|
|
|
reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
|
|
|
|
|
<0x30 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
|
|
|
reg-names = "regs", "config";
|
|
|
|
|
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
|
|
|
|
interrupt-names = "aer";
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
dma-coherent;
|
|
|
|
|
num-viewport = <6>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
|
|
|
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
|
|
|
msi-parent = <&its>;
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
|
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
2023-04-12 07:38:20 +00:00
|
|
|
status = "disabled";
|
2023-04-12 07:38:19 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcie_ep3: pcie-ep@3600000 {
|
|
|
|
|
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
|
|
|
|
|
reg = <0x00 0x03600000 0x0 0x00100000>,
|
|
|
|
|
<0x30 0x00000000 0x8 0x00000000>;
|
|
|
|
|
reg-names = "regs", "addr_space";
|
|
|
|
|
num-ib-windows = <6>;
|
|
|
|
|
num-ob-windows = <6>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:18 +00:00
|
|
|
smmu: iommu@5000000 {
|
|
|
|
|
compatible = "arm,mmu-500";
|
|
|
|
|
reg = <0 0x5000000 0 0x800000>;
|
|
|
|
|
#iommu-cells = <1>;
|
|
|
|
|
stream-match-mask = <0x7C00>;
|
|
|
|
|
dma-coherent;
|
|
|
|
|
#global-interrupts = <12>;
|
|
|
|
|
// global secure fault
|
|
|
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
// combined secure
|
|
|
|
|
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
// global non-secure fault
|
|
|
|
|
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
// combined non-secure
|
|
|
|
|
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
// performance counter interrupts 0-7
|
|
|
|
|
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
// per context interrupt, 64 interrupts
|
|
|
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
|
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
2023-04-12 07:38:25 +00:00
|
|
|
|
2023-04-12 07:38:28 +00:00
|
|
|
console@8340020 {
|
|
|
|
|
compatible = "fsl,dpaa2-console";
|
|
|
|
|
reg = <0x00000000 0x08340020 0 0x2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ptp-timer@8b95000 {
|
|
|
|
|
compatible = "fsl,dpaa2-ptp";
|
|
|
|
|
reg = <0x0 0x8b95000 0x0 0x100>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(1)>;
|
|
|
|
|
little-endian;
|
|
|
|
|
fsl,extts-fifo;
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:25 +00:00
|
|
|
emdio1: mdio@8b96000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0x0 0x8b96000 0x0 0x1000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-frequency = <2500000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(1)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
emdio2: mdio@8b97000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0x0 0x8b97000 0x0 0x1000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
clock-frequency = <2500000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(1)>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs_mdio1: mdio@8c07000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0x0 0x8c07000 0x0 0x1000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pcs1: ethernet-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs_mdio2: mdio@8c0b000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0x0 0x8c0b000 0x0 0x1000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pcs2: ethernet-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs_mdio3: mdio@8c0f000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0x0 0x8c0f000 0x0 0x1000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pcs3_0: ethernet-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs3_1: ethernet-phy@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs3_2: ethernet-phy@2 {
|
|
|
|
|
reg = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs3_3: ethernet-phy@3 {
|
|
|
|
|
reg = <3>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs_mdio7: mdio@8c1f000 {
|
|
|
|
|
compatible = "fsl,fman-memac-mdio";
|
|
|
|
|
reg = <0x0 0x8c1f000 0x0 0x1000>;
|
|
|
|
|
little-endian;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
|
|
|
|
|
pcs7_0: ethernet-phy@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs7_1: ethernet-phy@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs7_2: ethernet-phy@2 {
|
|
|
|
|
reg = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
pcs7_3: ethernet-phy@3 {
|
|
|
|
|
reg = <3>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2023-04-12 07:38:26 +00:00
|
|
|
|
2023-04-12 07:38:28 +00:00
|
|
|
cluster1_core0_watchdog: wdt@c000000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc000000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster1_core1_watchdog: wdt@c010000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc010000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster1_core2_watchdog: wdt@c020000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc020000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster1_core3_watchdog: wdt@c030000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc030000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster2_core0_watchdog: wdt@c100000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc100000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster2_core1_watchdog: wdt@c110000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc110000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster2_core2_watchdog: wdt@c120000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc120000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cluster2_core3_watchdog: wdt@c130000 {
|
|
|
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
|
|
|
reg = <0x0 0xc130000 0x0 0x1000>;
|
|
|
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>,
|
|
|
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
|
|
|
QORIQ_CLK_PLL_DIV(16)>;
|
|
|
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:26 +00:00
|
|
|
fsl_mc: fsl-mc@80c000000 {
|
|
|
|
|
compatible = "fsl,qoriq-mc";
|
|
|
|
|
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
|
|
|
|
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
|
|
|
|
msi-parent = <&its>;
|
|
|
|
|
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
|
|
|
|
|
dma-coherent;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Region type 0x0 - MC portals
|
|
|
|
|
* Region type 0x1 - QBMAN portals
|
|
|
|
|
*/
|
|
|
|
|
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
|
|
|
|
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
|
|
|
|
|
|
|
|
|
dpmacs {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
|
|
|
|
dpmac1: ethernet@1 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac2: ethernet@2 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac3: ethernet@3 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <3>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac4: ethernet@4 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <4>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac5: ethernet@5 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <5>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac6: ethernet@6 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <6>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac7: ethernet@7 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <7>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac8: ethernet@8 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <8>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac9: ethernet@9 {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <9>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dpmac10: ethernet@a {
|
|
|
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
|
|
|
reg = <0xa>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2023-04-12 07:38:28 +00:00
|
|
|
|
|
|
|
|
rcpm: power-controller@1e34040 {
|
|
|
|
|
compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
|
|
|
|
|
reg = <0x0 0x1e34040 0x0 0x18>;
|
|
|
|
|
#fsl,rcpm-wakeup-cells = <6>;
|
|
|
|
|
little-endian;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ftm_alarm0: timer@2800000 {
|
|
|
|
|
compatible = "fsl,ls1088a-ftm-alarm";
|
|
|
|
|
reg = <0x0 0x2800000 0x0 0x10000>;
|
|
|
|
|
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
|
|
|
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
2023-03-15 11:04:09 +00:00
|
|
|
};
|
|
|
|
|
|
2023-04-12 07:38:28 +00:00
|
|
|
firmware {
|
|
|
|
|
optee {
|
|
|
|
|
compatible = "linaro,optee-tz";
|
|
|
|
|
method = "smc";
|
|
|
|
|
};
|
2019-10-18 03:27:53 +00:00
|
|
|
};
|
armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
|
|
|
};
|
