ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Car Gen3 recovery SPL
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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2019-12-28 17:45:01 +00:00
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#include <cpu_func.h>
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2020-05-10 17:40:01 +00:00
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#include <image.h>
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2020-05-10 17:40:02 +00:00
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#include <init.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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#include <asm/io.h>
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#include <spl.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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#define RCAR_CNTC_BASE 0xE6080000
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#define CNTCR_EN BIT(0)
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void board_init_f(ulong dummy)
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{
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writel(CNTCR_EN, RCAR_CNTC_BASE);
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timer_init();
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}
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void spl_board_init(void)
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{
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_UART;
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}
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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debug("image entry point: 0x%lx\n", spl_image->entry_point);
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if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) {
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typedef void (*image_entry_arg_t)(int, int, int, int)
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__attribute__ ((noreturn));
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image_entry_arg_t image_entry =
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(image_entry_arg_t)(uintptr_t) spl_image->entry_point;
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image_entry(IH_MAGIC, CONFIG_SPL_TEXT_BASE, 0, 0);
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} else {
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typedef void __noreturn (*image_entry_noargs_t)(void);
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image_entry_noargs_t image_entry =
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(image_entry_noargs_t)spl_image->entry_point;
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image_entry();
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}
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}
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void s_init(void)
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{
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}
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2020-12-15 15:47:52 +00:00
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void reset_cpu(void)
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ARM: rmobile: Add recovery SPL for R-Car Gen3
Build an SPL which can be started via SCIF download mode on R-Car Gen3
and allows loading and executing U-Boot uImage with the next stage code.
This is also useful for starting e.g. ATF BL2, which inits the hardware
and returns to the U-Boot SPL, which can then load e.g. U-Boot proper.
The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL
while the payload, e.g. ATF BL2, executes, so there is no problem here.
However, E3 and D3 have much less SRAM, hence the loader uses a trick
where it copies itself beyond the area used by BL2 and executes from
there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS,
stack and malloc area, so the later two are placed at +0x4000 offset
from start of SRAM, another area not used by ATF BL2. To make things
even more complicated, the SCIF loader cannot load to the upper 32kiB
of the SRAM directly, hence the copying approach.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 10:44:13 +00:00
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{
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}
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