2021-06-02 07:58:23 +00:00
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd
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*/
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2022-09-02 13:10:52 +00:00
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#include "rockchip-u-boot.dtsi"
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2021-06-02 07:58:23 +00:00
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/ {
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aliases {
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mmc0 = &sdhci;
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mmc1 = &sdmmc0;
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};
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2021-10-26 02:42:20 +00:00
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chosen {
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2023-03-14 00:38:23 +00:00
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u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
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2021-10-26 02:42:20 +00:00
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};
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2021-06-02 07:58:23 +00:00
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dmc: dmc {
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compatible = "rockchip,rk3568-dmc";
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2021-06-02 07:58:23 +00:00
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status = "okay";
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};
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2023-02-22 22:44:41 +00:00
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otp: nvmem@fe38c000 {
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compatible = "rockchip,rk3568-otp";
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reg = <0x0 0xfe38c000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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cpu_id: id@a {
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reg = <0x0a 0x10>;
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};
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};
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2021-06-02 07:58:23 +00:00
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};
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&cru {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2021-06-02 07:58:23 +00:00
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status = "okay";
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};
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&pmucru {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2021-06-02 07:58:23 +00:00
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status = "okay";
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};
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&grf {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2021-06-02 07:58:23 +00:00
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status = "okay";
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};
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&pmugrf {
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2023-02-13 15:56:33 +00:00
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bootph-all;
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2021-06-02 07:58:23 +00:00
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status = "okay";
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};
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2021-10-26 02:42:20 +00:00
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2022-10-04 01:30:30 +00:00
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&sdhci {
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2023-02-13 15:56:33 +00:00
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bootph-pre-ram;
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2021-10-26 02:42:20 +00:00
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status = "okay";
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};
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2022-10-04 01:30:30 +00:00
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&sdmmc0 {
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2023-02-13 15:56:33 +00:00
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bootph-pre-ram;
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2021-10-26 02:42:20 +00:00
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status = "okay";
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};
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