2018-05-06 21:58:06 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-01-15 09:01:51 +00:00
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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2020-05-10 17:40:03 +00:00
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#include <command.h>
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2019-11-14 19:57:35 +00:00
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#include <cpu_func.h>
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2020-01-07 08:02:52 +00:00
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#include <debug_uart.h>
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2021-07-27 14:19:18 +00:00
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#include <dfu.h>
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2019-08-01 15:46:51 +00:00
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#include <env.h>
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2020-07-30 11:37:49 +00:00
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#include <env_internal.h>
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2019-11-14 19:57:46 +00:00
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#include <init.h>
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2021-05-31 09:03:19 +00:00
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#include <image.h>
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#include <lmb.h>
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2020-05-10 17:40:05 +00:00
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#include <log.h>
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2020-05-10 17:39:56 +00:00
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#include <net.h>
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2015-09-30 15:26:55 +00:00
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#include <sata.h>
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2015-07-23 11:27:40 +00:00
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#include <ahci.h>
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#include <scsi.h>
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2016-04-22 12:28:54 +00:00
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#include <malloc.h>
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2021-07-27 14:19:18 +00:00
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#include <memalign.h>
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2018-04-19 13:43:38 +00:00
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#include <wdt.h>
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2015-11-05 07:34:35 +00:00
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#include <asm/arch/clk.h>
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2015-01-15 09:01:51 +00:00
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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2018-01-10 08:36:09 +00:00
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#include <asm/arch/psu_init_gpl.h>
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2020-05-10 17:39:56 +00:00
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#include <asm/cache.h>
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2020-10-31 03:38:53 +00:00
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#include <asm/global_data.h>
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2015-01-15 09:01:51 +00:00
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#include <asm/io.h>
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2020-05-10 17:40:06 +00:00
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#include <asm/ptrace.h>
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2018-04-25 09:20:43 +00:00
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#include <dm/device.h>
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2018-04-19 13:43:38 +00:00
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#include <dm/uclass.h>
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2015-08-04 07:33:26 +00:00
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#include <usb.h>
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#include <dwc3-uboot.h>
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2016-02-01 14:05:58 +00:00
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#include <zynqmppl.h>
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2019-09-27 10:37:01 +00:00
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#include <zynqmp_firmware.h>
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2016-09-01 09:16:40 +00:00
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#include <g_dnl.h>
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2020-05-10 17:40:13 +00:00
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#include <linux/bitops.h>
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2020-05-10 17:40:11 +00:00
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#include <linux/delay.h>
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#include <linux/sizes.h>
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2020-03-31 10:39:37 +00:00
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#include "../common/board.h"
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2015-01-15 09:01:51 +00:00
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2019-05-21 16:06:43 +00:00
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#include "pm_cfg_obj.h"
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2020-08-04 22:17:31 +00:00
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#define ZYNQMP_VERSION_SIZE 7
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2020-10-21 10:23:17 +00:00
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#define EFUSE_VCU_DIS_MASK 0x100
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#define EFUSE_VCU_DIS_SHIFT 8
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#define EFUSE_GPU_DIS_MASK 0x20
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#define EFUSE_GPU_DIS_SHIFT 5
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#define IDCODE2_PL_INIT_MASK 0x200
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#define IDCODE2_PL_INIT_SHIFT 9
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2020-08-04 22:17:31 +00:00
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2015-01-15 09:01:51 +00:00
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DECLARE_GLOBAL_DATA_PTR;
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2020-09-09 12:41:56 +00:00
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#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
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2016-02-01 14:05:58 +00:00
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static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
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2020-08-04 22:17:31 +00:00
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enum {
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ZYNQMP_VARIANT_EG = BIT(0U),
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ZYNQMP_VARIANT_EV = BIT(1U),
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ZYNQMP_VARIANT_CG = BIT(2U),
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ZYNQMP_VARIANT_DR = BIT(3U),
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};
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2016-02-01 14:05:58 +00:00
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static const struct {
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2017-11-06 11:55:59 +00:00
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u32 id;
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2020-08-04 22:17:31 +00:00
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u8 device;
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u8 variants;
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2016-02-01 14:05:58 +00:00
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} zynqmp_devices[] = {
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04711093,
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.device = 2,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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2017-08-22 12:58:53 +00:00
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},
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2016-02-01 14:05:58 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04710093,
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.device = 3,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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2016-02-01 14:05:58 +00:00
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},
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2017-08-22 12:58:53 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04721093,
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.device = 4,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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2017-08-22 12:58:53 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04720093,
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.device = 5,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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2017-08-22 12:58:53 +00:00
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},
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2016-02-01 14:05:58 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04739093,
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.device = 6,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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2016-02-01 14:05:58 +00:00
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},
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2017-08-22 12:58:53 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04730093,
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.device = 7,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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2017-08-22 12:58:53 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04738093,
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.device = 9,
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2020-10-02 12:42:05 +00:00
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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2017-08-22 12:58:53 +00:00
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},
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2016-02-01 14:05:58 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04740093,
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.device = 11,
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.variants = ZYNQMP_VARIANT_EG,
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2016-02-01 14:05:58 +00:00
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},
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2017-08-22 12:58:53 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04750093,
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.device = 15,
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.variants = ZYNQMP_VARIANT_EG,
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2017-08-22 12:58:53 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04759093,
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.device = 17,
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.variants = ZYNQMP_VARIANT_EG,
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2017-08-22 12:58:53 +00:00
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},
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2016-02-01 14:05:58 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x04758093,
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.device = 19,
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.variants = ZYNQMP_VARIANT_EG,
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2016-02-01 14:05:58 +00:00
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},
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2017-08-22 12:58:53 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E1093,
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.device = 21,
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.variants = ZYNQMP_VARIANT_DR,
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2017-08-22 12:58:53 +00:00
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},
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2016-02-01 14:05:58 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E3093,
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.device = 23,
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.variants = ZYNQMP_VARIANT_DR,
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2016-02-01 14:05:58 +00:00
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},
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2017-08-22 12:58:53 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E5093,
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.device = 25,
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.variants = ZYNQMP_VARIANT_DR,
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2017-08-22 12:58:53 +00:00
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},
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2016-02-01 14:05:58 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E4093,
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.device = 27,
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.variants = ZYNQMP_VARIANT_DR,
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2016-02-01 14:05:58 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E0093,
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.device = 28,
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.variants = ZYNQMP_VARIANT_DR,
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2016-02-01 14:05:58 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E2093,
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.device = 29,
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.variants = ZYNQMP_VARIANT_DR,
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2016-02-01 14:05:58 +00:00
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},
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2017-06-02 06:08:59 +00:00
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047E6093,
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.device = 39,
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.variants = ZYNQMP_VARIANT_DR,
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2017-06-02 06:08:59 +00:00
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},
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{
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2020-09-11 07:22:15 +00:00
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.id = 0x047FD093,
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.device = 43,
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.variants = ZYNQMP_VARIANT_DR,
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2017-06-02 06:08:59 +00:00
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},
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{
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2020-09-11 07:22:15 +00:00
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.id = 0x047F8093,
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.device = 46,
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.variants = ZYNQMP_VARIANT_DR,
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2017-06-02 06:08:59 +00:00
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},
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{
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2020-09-11 07:22:15 +00:00
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.id = 0x047FF093,
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.device = 47,
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.variants = ZYNQMP_VARIANT_DR,
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2017-06-02 06:08:59 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047FB093,
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.device = 48,
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.variants = ZYNQMP_VARIANT_DR,
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2017-06-02 06:08:59 +00:00
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},
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{
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2020-08-04 22:17:31 +00:00
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.id = 0x047FE093,
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.device = 49,
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.variants = ZYNQMP_VARIANT_DR,
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2019-07-23 06:26:17 +00:00
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},
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2021-05-13 13:13:25 +00:00
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{
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.id = 0x046d0093,
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.device = 67,
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.variants = ZYNQMP_VARIANT_DR,
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},
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2016-02-01 14:05:58 +00:00
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};
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2020-10-05 07:35:40 +00:00
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static const struct {
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u32 id;
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char *name;
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} zynqmp_svd_devices[] = {
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{
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.id = 0x04714093,
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.name = "xck24"
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},
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{
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.id = 0x04724093,
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.name = "xck26",
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},
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};
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static char *zynqmp_detect_svd_name(u32 idcode)
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{
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u32 i;
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for (i = 0; i < ARRAY_SIZE(zynqmp_svd_devices); i++) {
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if (zynqmp_svd_devices[i].id == (idcode & 0x0FFFFFFF))
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return zynqmp_svd_devices[i].name;
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}
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return "unknown";
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}
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2016-02-01 14:05:58 +00:00
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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2020-08-04 22:17:31 +00:00
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u32 i;
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u32 idcode, idcode2;
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2020-08-05 10:41:35 +00:00
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char name[ZYNQMP_VERSION_SIZE];
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2020-08-04 22:17:30 +00:00
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u32 ret_payload[PAYLOAD_ARG_CNT];
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2020-10-07 13:13:17 +00:00
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int ret;
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2020-08-04 22:17:30 +00:00
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2020-10-21 10:16:02 +00:00
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ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
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if (ret) {
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debug("%s: Getting chipid failed\n", __func__);
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return "unknown";
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}
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2020-08-04 22:17:30 +00:00
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/*
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* Firmware returns:
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* payload[0][31:0] = status of the operation
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* payload[1]] = IDCODE
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* payload[2][19:0] = Version
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* payload[2][28:20] = EXTENDED_IDCODE
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* payload[2][29] = PL_INIT
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*/
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2020-08-04 22:17:31 +00:00
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idcode = ret_payload[1];
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idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
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2020-10-21 10:16:50 +00:00
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debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
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2020-08-04 22:17:31 +00:00
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idcode2);
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2017-08-22 12:58:53 +00:00
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2016-02-01 14:05:58 +00:00
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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2020-08-04 22:17:31 +00:00
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if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
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break;
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2016-02-01 14:05:58 +00:00
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}
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2018-03-02 10:50:10 +00:00
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if (i >= ARRAY_SIZE(zynqmp_devices))
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2020-10-05 07:35:40 +00:00
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return zynqmp_detect_svd_name(idcode);
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2018-03-02 10:50:10 +00:00
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2020-08-04 22:17:31 +00:00
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/* Add device prefix to the name */
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2020-10-07 13:13:17 +00:00
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ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
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zynqmp_devices[i].device);
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2020-10-21 10:17:44 +00:00
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if (ret < 0)
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2020-10-07 13:13:17 +00:00
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return "unknown";
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2018-03-02 10:50:10 +00:00
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2020-08-04 22:17:31 +00:00
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if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
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/* Devices with EV variant might be EG/CG/EV family */
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if (idcode2 & IDCODE2_PL_INIT_MASK) {
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u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
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EFUSE_VCU_DIS_SHIFT) << 1 |
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((idcode2 & EFUSE_GPU_DIS_MASK) >>
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EFUSE_GPU_DIS_SHIFT);
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2018-03-02 10:50:10 +00:00
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2020-08-04 22:17:31 +00:00
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/*
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* Get family name based on extended idcode values as
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* determined on UG1087, EXTENDED_IDCODE register
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* description
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|
|
|
*/
|
|
|
|
switch (family) {
|
|
|
|
case 0x00:
|
|
|
|
strncat(name, "ev", 2);
|
|
|
|
break;
|
|
|
|
case 0x10:
|
|
|
|
strncat(name, "eg", 2);
|
|
|
|
break;
|
|
|
|
case 0x11:
|
|
|
|
strncat(name, "cg", 2);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* Do not append family name*/
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* When PL powered down the VCU Disable efuse cannot be
|
|
|
|
* read. So, ignore the bit and just findout if it is CG
|
|
|
|
* or EG/EV variant.
|
|
|
|
*/
|
|
|
|
strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
|
|
|
|
"e", 2);
|
2018-10-26 12:17:55 +00:00
|
|
|
}
|
2020-08-04 22:17:31 +00:00
|
|
|
} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
|
|
|
|
/* Devices with CG variant might be EG or CG family */
|
|
|
|
strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
|
|
|
|
} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
|
|
|
|
strncat(name, "eg", 2);
|
|
|
|
} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
|
|
|
|
strncat(name, "dr", 2);
|
|
|
|
} else {
|
|
|
|
debug("Variant not identified\n");
|
2018-10-26 12:17:55 +00:00
|
|
|
}
|
|
|
|
|
2020-08-05 10:41:35 +00:00
|
|
|
return strdup(name);
|
2016-02-01 14:05:58 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2022-02-17 13:28:40 +00:00
|
|
|
#if defined(CONFIG_BOARD_EARLY_INIT_F)
|
2017-02-07 13:32:26 +00:00
|
|
|
int board_early_init_f(void)
|
|
|
|
{
|
2018-01-15 11:52:59 +00:00
|
|
|
#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
|
2020-01-07 08:02:52 +00:00
|
|
|
int ret;
|
|
|
|
|
2018-01-10 10:48:48 +00:00
|
|
|
ret = psu_init();
|
2020-01-07 08:02:52 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
2020-03-20 07:59:02 +00:00
|
|
|
|
2021-06-08 10:37:23 +00:00
|
|
|
/*
|
|
|
|
* PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
|
|
|
|
* supply sense channel to SysMon supply registers inside the IP.
|
|
|
|
* This register must be programmed to complete SysMon IP
|
|
|
|
* configuration. The default register configuration after
|
|
|
|
* power-up is incorrect. Hence, fix this by writing the
|
|
|
|
* correct value - 0x3210.
|
|
|
|
*/
|
|
|
|
writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
|
|
|
|
ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
|
|
|
|
|
2020-03-20 07:59:02 +00:00
|
|
|
/* Delay is required for clocks to be propagated */
|
|
|
|
udelay(1000000);
|
2017-07-12 11:08:41 +00:00
|
|
|
#endif
|
|
|
|
|
2020-01-07 08:02:52 +00:00
|
|
|
#ifdef CONFIG_DEBUG_UART
|
|
|
|
/* Uart debug for sure */
|
|
|
|
debug_uart_init();
|
|
|
|
puts("Debug uart enabled\n"); /* or printch() */
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
2017-02-07 13:32:26 +00:00
|
|
|
}
|
2022-02-17 13:28:40 +00:00
|
|
|
#endif
|
2017-02-07 13:32:26 +00:00
|
|
|
|
2020-02-11 11:43:14 +00:00
|
|
|
static int multi_boot(void)
|
|
|
|
{
|
2021-07-27 14:17:31 +00:00
|
|
|
u32 multiboot = 0;
|
|
|
|
int ret;
|
2020-02-11 11:43:14 +00:00
|
|
|
|
2021-07-27 14:17:31 +00:00
|
|
|
ret = zynqmp_mmio_read((ulong)&csu_base->multi_boot, &multiboot);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
2020-02-11 11:43:14 +00:00
|
|
|
|
2021-07-27 12:05:27 +00:00
|
|
|
return multiboot;
|
2020-02-11 11:43:14 +00:00
|
|
|
}
|
|
|
|
|
2021-10-13 13:48:00 +00:00
|
|
|
#if defined(CONFIG_SPL_BUILD)
|
|
|
|
static void restore_jtag(void)
|
|
|
|
{
|
|
|
|
if (current_el() != 3)
|
|
|
|
return;
|
|
|
|
|
|
|
|
writel(CSU_JTAG_SEC_GATE_DISABLE, &csu_base->jtag_sec);
|
|
|
|
writel(CSU_JTAG_DAP_ENABLE_DEBUG, &csu_base->jtag_dap_cfg);
|
|
|
|
writel(CSU_JTAG_CHAIN_WR_SETUP, &csu_base->jtag_chain_status_wr);
|
|
|
|
writel(CRLAPB_DBG_LPD_CTRL_SETUP_CLK, &crlapb_base->dbg_lpd_ctrl);
|
|
|
|
writel(CRLAPB_RST_LPD_DBG_RESET, &crlapb_base->rst_lpd_dbg);
|
|
|
|
writel(CSU_PCAP_PROG_RELEASE_PL, &csu_base->pcap_prog);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2021-10-13 17:04:47 +00:00
|
|
|
static void print_secure_boot(void)
|
|
|
|
{
|
|
|
|
u32 status = 0;
|
|
|
|
|
|
|
|
if (zynqmp_mmio_read((ulong)&csu_base->status, &status))
|
|
|
|
return;
|
|
|
|
|
|
|
|
printf("Secure Boot:\t%sauthenticated, %sencrypted\n",
|
|
|
|
status & ZYNQMP_CSU_STATUS_AUTHENTICATED ? "" : "not ",
|
|
|
|
status & ZYNQMP_CSU_STATUS_ENCRYPTED ? "" : "not ");
|
|
|
|
}
|
|
|
|
|
2019-10-18 05:34:13 +00:00
|
|
|
#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
|
|
|
|
#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
|
|
|
|
|
2015-01-15 09:01:51 +00:00
|
|
|
int board_init(void)
|
|
|
|
{
|
2020-03-04 07:48:16 +00:00
|
|
|
#if defined(CONFIG_ZYNQMP_FIRMWARE)
|
2019-09-27 10:37:04 +00:00
|
|
|
struct udevice *dev;
|
|
|
|
|
|
|
|
uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
|
|
|
|
if (!dev)
|
|
|
|
panic("PMU Firmware device not found - Enable it");
|
2020-03-04 07:48:16 +00:00
|
|
|
#endif
|
2019-09-27 10:37:04 +00:00
|
|
|
|
2019-05-21 16:06:43 +00:00
|
|
|
#if defined(CONFIG_SPL_BUILD)
|
|
|
|
/* Check *at build time* if the filename is an non-empty string */
|
|
|
|
if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
|
|
|
|
zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
|
|
|
|
zynqmp_pm_cfg_obj_size);
|
2021-02-02 15:34:48 +00:00
|
|
|
printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
|
2021-10-13 13:48:00 +00:00
|
|
|
|
|
|
|
/* the CSU disables the JTAG interface when secure boot is enabled */
|
2021-11-04 19:28:02 +00:00
|
|
|
if (CONFIG_IS_ENABLED(ZYNQMP_RESTORE_JTAG))
|
2021-10-13 13:48:00 +00:00
|
|
|
restore_jtag();
|
2020-08-03 11:01:45 +00:00
|
|
|
#else
|
|
|
|
if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
|
|
|
|
xilinx_read_eeprom();
|
2019-05-21 16:06:43 +00:00
|
|
|
#endif
|
|
|
|
|
2015-06-22 12:31:06 +00:00
|
|
|
printf("EL Level:\tEL%d\n", current_el());
|
|
|
|
|
2019-10-18 05:34:13 +00:00
|
|
|
/* Bug in ROM sets wrong value in this register */
|
|
|
|
writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
|
|
|
|
|
2020-09-09 12:41:56 +00:00
|
|
|
#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
|
2020-08-04 22:17:29 +00:00
|
|
|
zynqmppl.name = zynqmp_get_silicon_idcode_name();
|
|
|
|
printf("Chip ID:\t%s\n", zynqmppl.name);
|
|
|
|
fpga_init();
|
|
|
|
fpga_add(fpga_xilinx, &zynqmppl);
|
2016-02-01 14:05:58 +00:00
|
|
|
#endif
|
|
|
|
|
2021-10-13 17:04:47 +00:00
|
|
|
/* display secure boot information */
|
|
|
|
print_secure_boot();
|
2020-02-11 11:43:14 +00:00
|
|
|
if (current_el() == 3)
|
2021-07-27 12:05:27 +00:00
|
|
|
printf("Multiboot:\t%d\n", multi_boot());
|
2020-02-11 11:43:14 +00:00
|
|
|
|
2015-01-15 09:01:51 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int board_early_init_r(void)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
2017-12-07 09:35:30 +00:00
|
|
|
if (current_el() != 3)
|
|
|
|
return 0;
|
|
|
|
|
2017-07-12 08:32:18 +00:00
|
|
|
val = readl(&crlapb_base->timestamp_ref_ctrl);
|
|
|
|
val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
|
|
|
|
|
2017-12-07 09:35:30 +00:00
|
|
|
if (!val) {
|
2015-11-05 07:34:35 +00:00
|
|
|
val = readl(&crlapb_base->timestamp_ref_ctrl);
|
|
|
|
val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
|
|
|
|
writel(val, &crlapb_base->timestamp_ref_ctrl);
|
2015-01-15 09:01:51 +00:00
|
|
|
|
2015-11-05 07:34:35 +00:00
|
|
|
/* Program freq register in System counter */
|
|
|
|
writel(zynqmp_get_system_timer_freq(),
|
|
|
|
&iou_scntr_secure->base_frequency_id_register);
|
|
|
|
/* And enable system counter */
|
|
|
|
writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
|
|
|
|
&iou_scntr_secure->counter_control_register);
|
|
|
|
}
|
2015-01-15 09:01:51 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-02-16 07:26:17 +00:00
|
|
|
unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
|
2020-05-10 17:40:03 +00:00
|
|
|
char *const argv[])
|
2018-02-16 07:26:17 +00:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (current_el() > 1) {
|
|
|
|
smp_kick_all_cpus();
|
|
|
|
dcache_disable();
|
|
|
|
armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
|
|
|
|
ES_TO_AARCH64);
|
|
|
|
} else {
|
|
|
|
printf("FAIL: current EL is not above EL1\n");
|
|
|
|
ret = EINVAL;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2016-02-08 08:34:53 +00:00
|
|
|
#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
|
2017-03-31 14:40:32 +00:00
|
|
|
int dram_init_banksize(void)
|
2016-12-09 12:56:54 +00:00
|
|
|
{
|
2018-04-20 07:00:40 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = fdtdec_setup_memory_banksize();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
mem_map_fill();
|
|
|
|
|
|
|
|
return 0;
|
2016-12-06 15:31:53 +00:00
|
|
|
}
|
2016-02-08 08:34:53 +00:00
|
|
|
|
2016-12-09 12:56:54 +00:00
|
|
|
int dram_init(void)
|
2016-12-06 15:31:53 +00:00
|
|
|
{
|
2018-07-16 10:26:11 +00:00
|
|
|
if (fdtdec_setup_mem_size_base() != 0)
|
2016-12-18 14:03:34 +00:00
|
|
|
return -EINVAL;
|
2016-12-06 15:31:53 +00:00
|
|
|
|
2016-12-09 12:56:54 +00:00
|
|
|
return 0;
|
2016-02-08 08:34:53 +00:00
|
|
|
}
|
2021-05-31 09:03:19 +00:00
|
|
|
|
|
|
|
ulong board_get_usable_ram_top(ulong total_size)
|
|
|
|
{
|
|
|
|
phys_size_t size;
|
|
|
|
phys_addr_t reg;
|
|
|
|
struct lmb lmb;
|
|
|
|
|
2021-08-19 09:07:59 +00:00
|
|
|
if (!IS_ALIGNED((ulong)gd->fdt_blob, 0x8))
|
|
|
|
panic("Not 64bit aligned DT location: %p\n", gd->fdt_blob);
|
|
|
|
|
2021-05-31 09:03:19 +00:00
|
|
|
/* found enough not-reserved memory to relocated U-Boot */
|
|
|
|
lmb_init(&lmb);
|
|
|
|
lmb_add(&lmb, gd->ram_base, gd->ram_size);
|
|
|
|
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
|
2021-10-21 06:58:50 +00:00
|
|
|
size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE);
|
2021-05-31 09:03:19 +00:00
|
|
|
reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
|
|
|
|
|
|
|
|
if (!reg)
|
|
|
|
reg = gd->ram_top - size;
|
|
|
|
|
|
|
|
return reg + size;
|
|
|
|
}
|
2016-02-08 08:34:53 +00:00
|
|
|
#else
|
2018-04-20 07:00:40 +00:00
|
|
|
int dram_init_banksize(void)
|
|
|
|
{
|
|
|
|
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
|
|
|
|
gd->bd->bi_dram[0].size = get_effective_memsize();
|
|
|
|
|
|
|
|
mem_map_fill();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-01-15 09:01:51 +00:00
|
|
|
int dram_init(void)
|
|
|
|
{
|
2018-04-11 14:12:28 +00:00
|
|
|
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
|
|
|
|
CONFIG_SYS_SDRAM_SIZE);
|
2015-01-15 09:01:51 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2016-02-08 08:34:53 +00:00
|
|
|
#endif
|
2015-01-15 09:01:51 +00:00
|
|
|
|
2021-07-13 14:39:26 +00:00
|
|
|
#if !CONFIG_IS_ENABLED(SYSRESET)
|
2020-12-15 15:47:52 +00:00
|
|
|
void reset_cpu(void)
|
2015-01-15 09:01:51 +00:00
|
|
|
{
|
|
|
|
}
|
2021-07-13 14:39:26 +00:00
|
|
|
#endif
|
2015-01-15 09:01:51 +00:00
|
|
|
|
2020-08-20 08:54:45 +00:00
|
|
|
static u8 __maybe_unused zynqmp_get_bootmode(void)
|
|
|
|
{
|
|
|
|
u8 bootmode;
|
|
|
|
u32 reg = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2021-07-28 10:25:49 +00:00
|
|
|
debug("HW boot mode: %x\n", reg & BOOT_MODES_MASK);
|
|
|
|
debug("ALT boot mode: %x\n", reg >> BOOT_MODE_ALT_SHIFT);
|
|
|
|
|
2020-08-20 08:54:45 +00:00
|
|
|
if (reg >> BOOT_MODE_ALT_SHIFT)
|
|
|
|
reg >>= BOOT_MODE_ALT_SHIFT;
|
|
|
|
|
|
|
|
bootmode = reg & BOOT_MODES_MASK;
|
|
|
|
|
|
|
|
return bootmode;
|
|
|
|
}
|
|
|
|
|
2018-12-20 08:33:38 +00:00
|
|
|
#if defined(CONFIG_BOARD_LATE_INIT)
|
2018-05-17 12:06:06 +00:00
|
|
|
static const struct {
|
|
|
|
u32 bit;
|
|
|
|
const char *name;
|
|
|
|
} reset_reasons[] = {
|
|
|
|
{ RESET_REASON_DEBUG_SYS, "DEBUG" },
|
|
|
|
{ RESET_REASON_SOFT, "SOFT" },
|
|
|
|
{ RESET_REASON_SRST, "SRST" },
|
|
|
|
{ RESET_REASON_PSONLY, "PS-ONLY" },
|
|
|
|
{ RESET_REASON_PMU, "PMU" },
|
|
|
|
{ RESET_REASON_INTERNAL, "INTERNAL" },
|
|
|
|
{ RESET_REASON_EXTERNAL, "EXTERNAL" },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2019-03-13 14:54:18 +00:00
|
|
|
static int reset_reason(void)
|
2018-05-17 12:06:06 +00:00
|
|
|
{
|
2019-03-13 14:54:18 +00:00
|
|
|
u32 reg;
|
|
|
|
int i, ret;
|
2018-05-17 12:06:06 +00:00
|
|
|
const char *reason = NULL;
|
|
|
|
|
2019-03-13 14:54:18 +00:00
|
|
|
ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
|
|
|
|
if (ret)
|
|
|
|
return -EINVAL;
|
2018-05-17 12:06:06 +00:00
|
|
|
|
|
|
|
puts("Reset reason:\t");
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
|
2019-03-13 14:54:18 +00:00
|
|
|
if (reg & reset_reasons[i].bit) {
|
2018-05-17 12:06:06 +00:00
|
|
|
reason = reset_reasons[i].name;
|
|
|
|
printf("%s ", reset_reasons[i].name);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
puts("\n");
|
|
|
|
|
|
|
|
env_set("reset_reason", reason);
|
|
|
|
|
2021-02-09 07:50:22 +00:00
|
|
|
return 0;
|
2018-05-17 12:06:06 +00:00
|
|
|
}
|
|
|
|
|
2019-02-14 12:14:30 +00:00
|
|
|
static int set_fdtfile(void)
|
|
|
|
{
|
|
|
|
char *compatible, *fdtfile;
|
|
|
|
const char *suffix = ".dtb";
|
|
|
|
const char *vendor = "xilinx/";
|
2020-06-24 12:33:46 +00:00
|
|
|
int fdt_compat_len;
|
2019-02-14 12:14:30 +00:00
|
|
|
|
|
|
|
if (env_get("fdtfile"))
|
|
|
|
return 0;
|
|
|
|
|
2020-06-24 12:33:46 +00:00
|
|
|
compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
|
|
|
|
&fdt_compat_len);
|
|
|
|
if (compatible && fdt_compat_len) {
|
|
|
|
char *name;
|
|
|
|
|
2019-02-14 12:14:30 +00:00
|
|
|
debug("Compatible: %s\n", compatible);
|
|
|
|
|
2020-06-24 12:33:46 +00:00
|
|
|
name = strchr(compatible, ',');
|
|
|
|
if (!name)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
name++;
|
2019-02-14 12:14:30 +00:00
|
|
|
|
2020-06-24 12:33:46 +00:00
|
|
|
fdtfile = calloc(1, strlen(vendor) + strlen(name) +
|
2019-02-14 12:14:30 +00:00
|
|
|
strlen(suffix) + 1);
|
|
|
|
if (!fdtfile)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2020-06-24 12:33:46 +00:00
|
|
|
sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
|
2019-02-14 12:14:30 +00:00
|
|
|
|
|
|
|
env_set("fdtfile", fdtfile);
|
|
|
|
free(fdtfile);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-08 09:04:41 +00:00
|
|
|
int board_late_init(void)
|
|
|
|
{
|
2015-01-15 09:01:51 +00:00
|
|
|
u8 bootmode;
|
2018-04-25 09:20:43 +00:00
|
|
|
struct udevice *dev;
|
|
|
|
int bootseq = -1;
|
|
|
|
int bootseq_len = 0;
|
2018-04-25 09:10:34 +00:00
|
|
|
int env_targets_len = 0;
|
2016-04-22 12:28:54 +00:00
|
|
|
const char *mode;
|
|
|
|
char *new_targets;
|
2017-12-20 11:05:06 +00:00
|
|
|
char *env_targets;
|
2021-10-25 08:10:52 +00:00
|
|
|
int ret, multiboot;
|
2016-04-22 12:28:54 +00:00
|
|
|
|
2018-10-05 06:55:16 +00:00
|
|
|
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
|
|
|
|
usb_ether_init();
|
|
|
|
#endif
|
|
|
|
|
2016-04-22 12:28:54 +00:00
|
|
|
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
|
|
|
|
debug("Saved variables - Skipping\n");
|
|
|
|
return 0;
|
|
|
|
}
|
2015-01-15 09:01:51 +00:00
|
|
|
|
2020-07-28 10:45:47 +00:00
|
|
|
if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
|
|
|
|
return 0;
|
|
|
|
|
2019-02-14 12:14:30 +00:00
|
|
|
ret = set_fdtfile();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2021-10-25 08:10:52 +00:00
|
|
|
multiboot = multi_boot();
|
|
|
|
if (multiboot >= 0)
|
|
|
|
env_set_hex("multiboot", multiboot);
|
|
|
|
|
2020-04-08 09:04:41 +00:00
|
|
|
bootmode = zynqmp_get_bootmode();
|
2015-01-15 09:01:51 +00:00
|
|
|
|
2015-09-20 15:20:42 +00:00
|
|
|
puts("Bootmode: ");
|
2015-01-15 09:01:51 +00:00
|
|
|
switch (bootmode) {
|
2016-08-19 12:14:52 +00:00
|
|
|
case USB_MODE:
|
|
|
|
puts("USB_MODE\n");
|
2021-03-25 05:37:57 +00:00
|
|
|
mode = "usb_dfu0 usb_dfu1";
|
2017-12-01 14:18:24 +00:00
|
|
|
env_set("modeboot", "usb_dfu_spl");
|
2016-08-19 12:14:52 +00:00
|
|
|
break;
|
2015-03-13 05:40:26 +00:00
|
|
|
case JTAG_MODE:
|
2015-09-20 15:20:42 +00:00
|
|
|
puts("JTAG_MODE\n");
|
2019-06-25 12:11:09 +00:00
|
|
|
mode = "jtag pxe dhcp";
|
2017-12-01 14:18:24 +00:00
|
|
|
env_set("modeboot", "jtagboot");
|
2015-03-13 05:40:26 +00:00
|
|
|
break;
|
|
|
|
case QSPI_MODE_24BIT:
|
|
|
|
case QSPI_MODE_32BIT:
|
2016-04-22 12:28:54 +00:00
|
|
|
mode = "qspi0";
|
2015-09-20 15:20:42 +00:00
|
|
|
puts("QSPI_MODE\n");
|
2017-12-01 14:18:24 +00:00
|
|
|
env_set("modeboot", "qspiboot");
|
2015-03-13 05:40:26 +00:00
|
|
|
break;
|
2015-04-15 13:02:28 +00:00
|
|
|
case EMMC_MODE:
|
2015-10-05 13:59:38 +00:00
|
|
|
puts("EMMC_MODE\n");
|
2019-12-17 13:41:42 +00:00
|
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
|
|
"mmc@ff160000", &dev) &&
|
|
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
|
|
"sdhci@ff160000", &dev)) {
|
|
|
|
puts("Boot from EMMC but without SD0 enabled!\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2020-12-17 04:20:07 +00:00
|
|
|
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
|
2019-12-17 13:41:42 +00:00
|
|
|
|
|
|
|
mode = "mmc";
|
2020-12-17 04:20:07 +00:00
|
|
|
bootseq = dev_seq(dev);
|
2021-09-15 06:52:17 +00:00
|
|
|
env_set("modeboot", "emmcboot");
|
2015-10-05 13:59:38 +00:00
|
|
|
break;
|
|
|
|
case SD_MODE:
|
2015-09-20 15:20:42 +00:00
|
|
|
puts("SD_MODE\n");
|
2018-04-25 09:20:43 +00:00
|
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
2019-01-03 10:14:24 +00:00
|
|
|
"mmc@ff160000", &dev) &&
|
|
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
2018-04-25 09:20:43 +00:00
|
|
|
"sdhci@ff160000", &dev)) {
|
|
|
|
puts("Boot from SD0 but without SD0 enabled!\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2020-12-17 04:20:07 +00:00
|
|
|
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
|
2018-04-25 09:20:43 +00:00
|
|
|
|
|
|
|
mode = "mmc";
|
2020-12-17 04:20:07 +00:00
|
|
|
bootseq = dev_seq(dev);
|
2017-12-01 14:18:24 +00:00
|
|
|
env_set("modeboot", "sdboot");
|
2015-01-15 09:01:51 +00:00
|
|
|
break;
|
2016-09-21 06:15:05 +00:00
|
|
|
case SD1_LSHFT_MODE:
|
|
|
|
puts("LVL_SHFT_");
|
2021-10-18 11:30:04 +00:00
|
|
|
fallthrough;
|
2015-10-05 08:51:12 +00:00
|
|
|
case SD_MODE1:
|
2015-09-20 15:20:42 +00:00
|
|
|
puts("SD_MODE1\n");
|
2018-04-25 09:20:43 +00:00
|
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
2019-01-03 10:14:24 +00:00
|
|
|
"mmc@ff170000", &dev) &&
|
|
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
2018-04-25 09:20:43 +00:00
|
|
|
"sdhci@ff170000", &dev)) {
|
|
|
|
puts("Boot from SD1 but without SD1 enabled!\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2020-12-17 04:20:07 +00:00
|
|
|
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
|
2018-04-25 09:20:43 +00:00
|
|
|
|
|
|
|
mode = "mmc";
|
2020-12-17 04:20:07 +00:00
|
|
|
bootseq = dev_seq(dev);
|
2017-12-01 14:18:24 +00:00
|
|
|
env_set("modeboot", "sdboot");
|
2015-10-05 08:51:12 +00:00
|
|
|
break;
|
|
|
|
case NAND_MODE:
|
2015-09-20 15:20:42 +00:00
|
|
|
puts("NAND_MODE\n");
|
2016-04-22 12:28:54 +00:00
|
|
|
mode = "nand0";
|
2017-12-01 14:18:24 +00:00
|
|
|
env_set("modeboot", "nandboot");
|
2015-10-05 08:51:12 +00:00
|
|
|
break;
|
2015-01-15 09:01:51 +00:00
|
|
|
default:
|
2016-04-22 12:28:54 +00:00
|
|
|
mode = "";
|
2015-01-15 09:01:51 +00:00
|
|
|
printf("Invalid Boot Mode:0x%x\n", bootmode);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-04-25 09:20:43 +00:00
|
|
|
if (bootseq >= 0) {
|
|
|
|
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
|
|
|
|
debug("Bootseq len: %x\n", bootseq_len);
|
2021-01-11 12:46:58 +00:00
|
|
|
env_set_hex("bootseq", bootseq);
|
2018-04-25 09:20:43 +00:00
|
|
|
}
|
|
|
|
|
2016-04-22 12:28:54 +00:00
|
|
|
/*
|
|
|
|
* One terminating char + one byte for space between mode
|
|
|
|
* and default boot_targets
|
|
|
|
*/
|
2017-12-20 11:05:06 +00:00
|
|
|
env_targets = env_get("boot_targets");
|
2018-04-25 09:10:34 +00:00
|
|
|
if (env_targets)
|
|
|
|
env_targets_len = strlen(env_targets);
|
|
|
|
|
2018-04-25 09:20:43 +00:00
|
|
|
new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
|
|
|
|
bootseq_len);
|
2018-06-13 07:42:41 +00:00
|
|
|
if (!new_targets)
|
|
|
|
return -ENOMEM;
|
2018-04-25 09:10:34 +00:00
|
|
|
|
2018-04-25 09:20:43 +00:00
|
|
|
if (bootseq >= 0)
|
|
|
|
sprintf(new_targets, "%s%x %s", mode, bootseq,
|
|
|
|
env_targets ? env_targets : "");
|
|
|
|
else
|
|
|
|
sprintf(new_targets, "%s %s", mode,
|
|
|
|
env_targets ? env_targets : "");
|
2016-04-22 12:28:54 +00:00
|
|
|
|
2017-08-03 18:22:09 +00:00
|
|
|
env_set("boot_targets", new_targets);
|
2021-07-28 10:46:39 +00:00
|
|
|
free(new_targets);
|
2016-04-22 12:28:54 +00:00
|
|
|
|
2018-05-17 12:06:06 +00:00
|
|
|
reset_reason();
|
|
|
|
|
2020-03-31 10:39:37 +00:00
|
|
|
return board_late_init_xilinx();
|
2015-01-15 09:01:51 +00:00
|
|
|
}
|
2018-12-20 08:33:38 +00:00
|
|
|
#endif
|
2015-08-04 07:31:05 +00:00
|
|
|
|
|
|
|
int checkboard(void)
|
|
|
|
{
|
2016-01-25 10:04:21 +00:00
|
|
|
puts("Board: Xilinx ZynqMP\n");
|
2015-08-04 07:31:05 +00:00
|
|
|
return 0;
|
|
|
|
}
|
2020-07-30 11:37:49 +00:00
|
|
|
|
2021-05-19 13:16:19 +00:00
|
|
|
int mmc_get_env_dev(void)
|
|
|
|
{
|
|
|
|
struct udevice *dev;
|
|
|
|
int bootseq = 0;
|
|
|
|
|
|
|
|
switch (zynqmp_get_bootmode()) {
|
|
|
|
case EMMC_MODE:
|
|
|
|
case SD_MODE:
|
|
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
|
|
"mmc@ff160000", &dev) &&
|
|
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
|
|
"sdhci@ff160000", &dev)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
bootseq = dev_seq(dev);
|
|
|
|
break;
|
|
|
|
case SD1_LSHFT_MODE:
|
|
|
|
case SD_MODE1:
|
|
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
|
|
"mmc@ff170000", &dev) &&
|
|
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
|
|
"sdhci@ff170000", &dev)) {
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
bootseq = dev_seq(dev);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
debug("bootseq %d\n", bootseq);
|
|
|
|
|
|
|
|
return bootseq;
|
|
|
|
}
|
|
|
|
|
2020-07-30 11:37:49 +00:00
|
|
|
enum env_location env_get_location(enum env_operation op, int prio)
|
|
|
|
{
|
|
|
|
u32 bootmode = zynqmp_get_bootmode();
|
|
|
|
|
|
|
|
if (prio)
|
|
|
|
return ENVL_UNKNOWN;
|
|
|
|
|
|
|
|
switch (bootmode) {
|
|
|
|
case EMMC_MODE:
|
|
|
|
case SD_MODE:
|
|
|
|
case SD1_LSHFT_MODE:
|
|
|
|
case SD_MODE1:
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
|
|
|
|
return ENVL_FAT;
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
|
|
|
|
return ENVL_EXT4;
|
2021-07-02 08:28:36 +00:00
|
|
|
return ENVL_NOWHERE;
|
2020-07-30 11:37:49 +00:00
|
|
|
case NAND_MODE:
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
|
|
|
|
return ENVL_NAND;
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
|
|
|
|
return ENVL_UBI;
|
2021-07-02 08:28:36 +00:00
|
|
|
return ENVL_NOWHERE;
|
2020-07-30 11:37:49 +00:00
|
|
|
case QSPI_MODE_24BIT:
|
|
|
|
case QSPI_MODE_32BIT:
|
|
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
|
|
|
|
return ENVL_SPI_FLASH;
|
2021-07-02 08:28:36 +00:00
|
|
|
return ENVL_NOWHERE;
|
2020-07-30 11:37:49 +00:00
|
|
|
case JTAG_MODE:
|
|
|
|
default:
|
|
|
|
return ENVL_NOWHERE;
|
|
|
|
}
|
|
|
|
}
|
2021-07-27 14:19:18 +00:00
|
|
|
|
|
|
|
#if defined(CONFIG_SET_DFU_ALT_INFO)
|
|
|
|
|
|
|
|
#define DFU_ALT_BUF_LEN SZ_1K
|
|
|
|
|
|
|
|
void set_dfu_alt_info(char *interface, char *devstr)
|
|
|
|
{
|
|
|
|
u8 multiboot;
|
|
|
|
int bootseq = 0;
|
|
|
|
|
|
|
|
ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN);
|
|
|
|
|
|
|
|
if (env_get("dfu_alt_info"))
|
|
|
|
return;
|
|
|
|
|
|
|
|
memset(buf, 0, sizeof(buf));
|
|
|
|
|
|
|
|
multiboot = multi_boot();
|
2021-10-25 08:10:52 +00:00
|
|
|
if (multiboot < 0)
|
|
|
|
multiboot = 0;
|
|
|
|
|
|
|
|
multiboot = env_get_hex("multiboot", multiboot);
|
2021-07-27 14:19:18 +00:00
|
|
|
debug("Multiboot: %d\n", multiboot);
|
|
|
|
|
|
|
|
switch (zynqmp_get_bootmode()) {
|
|
|
|
case EMMC_MODE:
|
|
|
|
case SD_MODE:
|
|
|
|
case SD1_LSHFT_MODE:
|
|
|
|
case SD_MODE1:
|
|
|
|
bootseq = mmc_get_env_dev();
|
|
|
|
if (!multiboot)
|
|
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
|
|
"mmc %d:1=boot.bin fat %d 1;"
|
2021-10-18 12:02:15 +00:00
|
|
|
"%s fat %d 1",
|
|
|
|
bootseq, bootseq,
|
|
|
|
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
|
2021-07-27 14:19:18 +00:00
|
|
|
else
|
|
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
|
|
"mmc %d:1=boot%04d.bin fat %d 1;"
|
2021-10-18 12:02:15 +00:00
|
|
|
"%s fat %d 1",
|
|
|
|
bootseq, multiboot, bootseq,
|
|
|
|
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, bootseq);
|
2021-07-27 14:19:18 +00:00
|
|
|
break;
|
|
|
|
case QSPI_MODE_24BIT:
|
|
|
|
case QSPI_MODE_32BIT:
|
|
|
|
snprintf(buf, DFU_ALT_BUF_LEN,
|
|
|
|
"sf 0:0=boot.bin raw %x 0x1500000;"
|
2021-10-18 12:02:15 +00:00
|
|
|
"%s raw 0x%x 0x500000",
|
|
|
|
multiboot * SZ_32K, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME,
|
|
|
|
CONFIG_SYS_SPI_U_BOOT_OFFS);
|
2021-07-27 14:19:18 +00:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
env_set("dfu_alt_info", buf);
|
|
|
|
puts("DFU alt info setting: done\n");
|
|
|
|
}
|
|
|
|
#endif
|