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Author SHA1 Message Date
Sven Peter
148fe31122 exception_asm.S: correctly setup sp for EL1 
The previous code switched SPSel to EL0 but then used eret to
jump to EL1h which uses SP_EL1 instead

Signed-off-by: Sven Peter <sven@svenpeter.dev>
 2021-05-11 15:48:40 +09:00
Hector Martin
9a7a5c86a5 hv.py: Map only from guest base to RAM top to guest 
This keeps the hypervisor safe, in theory.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
a6287ae68d proxy.py: Add defaults to hv_translate flag args 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
19415bd6a5 run_guest.py: Support setting boot_args 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
3fecf181f9 proxyutils.py: Only decode abort/msr info for SYNC exceptions 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
9bfe278f52 proxyutils.py: Add disassemble_at() method 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
e3d7e569dc sysreg.py: Define an impdef EC code that Apple seems to use 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
6ad3b263a1 macho.py: Add support for loaded section hooks for patching 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
ed32cf6328 hv_exc: Add a hacky STEP feature to interrupt guest after a while 
This should eventually be a proper single step feature or something, but
for now...

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
bcdafe8d00 hv_vm: Short-circuit hv_translate when MMU is off 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
8d5596a1a1 hv_vm: Fix bug when making L2 mappings 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
52823eaab6 hv_asm: Turn off PAN on exception entry 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
4c043a0f97 memory: Move SCTLR/TCR defines to arm_cpu_regs.h 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
aadf54d86f proxy.py: Add missing FB defines 
Also fix some calls

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-09 03:25:51 +09:00
Hector Martin
f58a9774d2 hv.py: Shut down fb before entering guest 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-08 03:43:59 +09:00
Hector Martin
0203aa6d3d proxy: Add framebuffer ops 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-08 03:42:21 +09:00
Hector Martin
8a8a004d48 hv.py: Correctly declare BootArgs in ADT memory map 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-08 02:40:57 +09:00
Hector Martin
530069bbfa proxyutils.py: Switch to gzip compression for writemem_compressed 
lzma is too slow, not worth the gain now that we have USB.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-08 02:40:13 +09:00
Hector Martin
36a6c9de3e proxy.py: Correctly indicate USB reconnection timeout 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-08 02:39:56 +09:00
Hector Martin
adb91b4374 chainload.py: Add support for setting boot-args 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-08 02:39:32 +09:00
Hector Martin
aad892d461 fb: Implement fb_shutdown() & friends 
Clean up after ourselves before chainload

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-07 12:19:20 +09:00
Hector Martin
c6965acc75 adt.py: Fix typo 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-06 23:36:29 +09:00
Hector Martin
f1cc65f6c0 chainload.py: Set up SEPFW address in ADT 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-06 03:33:35 +09:00
Hector Martin
bbbea9db34 proxyutils: Disable serial timeout for writemem_compressed 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-06 03:32:39 +09:00
Hector Martin
0ae3455d51 hv_vuart: World's stupidest virtual UART implementation 
Work in progress...

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 04:03:44 +09:00
Hector Martin
9407dba2e0 hv_vm: Initial data abort handling 
Supports software-mapping for a subset of ldr/str instructions.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 04:03:44 +09:00
Hector Martin
8a64441bcd hv_vm: Extend hv_translate() for stage1 and write modes 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 03:27:19 +09:00
Hector Martin
c0c7c57dd0 hv_vm: Fix bug inhv_pt_map_l4() 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 03:24:37 +09:00
Hector Martin
ce3a673413 uart: Move registers to uart_regs.h 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 03:23:25 +09:00
Hector Martin
27af846aae hv_vm.c: Move SPTE_TYPE to bit 50 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 03:23:04 +09:00
Hector Martin
0e987f031b utils: Add flush_and_reboot() to do the iodev flush dance 
Use this for exceptions, asserts, etc.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 03:21:48 +09:00
Hector Martin
76b690e767 hv.py: Make ^D exit the hypervisor, not cont 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 00:46:53 +09:00
Hector Martin
4b3f527de9 proxyutils: Disassemble faulting code on exceptions 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 00:46:48 +09:00
Hector Martin
652c7e27a1 proxyutils.py: u.inst -> u.exec and support assembly 
Also refactor mrs/msr in terms of u.exec.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 00:28:39 +09:00
Hector Martin
50f112c396 hv: Add support for address translation & abort decoding 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 00:28:39 +09:00
Hector Martin
a3440f2b48 hv: Support cleanly exiting the hypervisor from an exception 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 00:28:39 +09:00
Hector Martin
d35fa5e0fc iodev: Add iodev_console_kick() 
This is used prior to rebooting in exception handlers, to make sure all
the exception dump data gets sent to USB if we are connected via that.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-05 00:28:39 +09:00
Hector Martin
5ad0bdf994 sysreg: Fix ESR_ISS_MSR.CRm field bounds 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 23:01:55 +09:00
Hector Martin
78895edf2c hv.py: Properly copy ADT and TrustCache into guest region 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 22:57:08 +09:00
Hector Martin
954408cc65 chainload: Support old-school call based chainloading 
This is useful in the middle of the HV exception handler to reboot m1n1
entirely, since we can't do a clean exit the way we would for normal
chainloading.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 22:56:47 +09:00
Hector Martin
826bdb709c sysreg.py: Correct SPSR definition for AArch64 mode 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 20:05:54 +09:00
Hector Martin
4d64c33ca6 hv: Implement basic exception handling 
Allows Python to handle hypervisor exceptions, and implements exception
info display and basic debug commands.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:36:23 +09:00
Hector Martin
b015dcf272 shell.py: Make usable as a module 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:35:19 +09:00
Hector Martin
315fcf36aa uartproxy: Add support for nested invocations 
This allows the proxy to call back to Python for handling exceptions or
other events, passing reason information about why it was invoked and
returning normally when the exception has been handled.

Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:34:08 +09:00
Hector Martin
38b716c33c hv.py: Do not fail if ADT was already mutated 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:32:18 +09:00
Hector Martin
23c723003f sysreg.py: Move sysreg definitions here from proxyutils 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:31:41 +09:00
Hector Martin
35d564801a utils.py: Add Register class to handle register fields 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:26:41 +09:00
Hector Martin
4cc0f45c9d arm_cpu_regs.h: Add SYS_ESR_EL2 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:25:46 +09:00
Hector Martin
785dba33ad exception_asm: Fix missing register restores 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:24:52 +09:00
Hector Martin
a326aca956 hv: Enable physical timer for EL1 properly 
Signed-off-by: Hector Martin <marcan@marcan.st>
 2021-05-04 19:23:35 +09:00