mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-22 14:43:08 +00:00
memory: Move SCTLR/TCR defines to arm_cpu_regs.h
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
aadf54d86f
commit
4c043a0f97
2 changed files with 107 additions and 38 deletions
|
|
@ -151,6 +151,54 @@
|
|||
#define PAR_PTW BIT(8)
|
||||
#define PAR_FST GENMASK(6, 1)
|
||||
|
||||
#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
|
||||
#define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
|
||||
#define SCTLR_EPAN BIT(57)
|
||||
#define SCTLR_EnALS BIT(56)
|
||||
#define SCTLR_EnAS0 BIT(55)
|
||||
#define SCTLR_EnASR BIT(54)
|
||||
#define SCTLR_TWEDEL GENMASK(49, 46)
|
||||
#define SCTLR_TWEDEn BIT(45)
|
||||
#define SCTLR_DSSBS BIT(44)
|
||||
#define SCTLR_ATA BIT(43)
|
||||
#define SCTLR_ATA0 BIT(42)
|
||||
#define SCTLR_TCF GENMASK(41, 40)
|
||||
#define SCTLR_TCF0 GENMASK(39, 38)
|
||||
#define SCTLR_ITFSB BIT(37)
|
||||
#define SCTLR_BT1 BIT(36)
|
||||
#define SCTLR_BT0 BIT(35)
|
||||
#define SCTLR_EnIA BIT(31)
|
||||
#define SCTLR_EnIB BIT(30)
|
||||
#define SCTLR_LSMAOE BIT(29)
|
||||
#define SCTLR_nTLSMD BIT(28)
|
||||
#define SCTLR_EnDA BIT(27)
|
||||
#define SCTLR_UCI BIT(26)
|
||||
#define SCTLR_EE BIT(25)
|
||||
#define SCTLR_E0E BIT(24)
|
||||
#define SCTLR_SPAN BIT(23)
|
||||
#define SCTLR_EIS BIT(22)
|
||||
#define SCTLR_IESB BIT(21)
|
||||
#define SCTLR_TSCXT BIT(20)
|
||||
#define SCTLR_WXN BIT(19)
|
||||
#define SCTLR_nTWE BIT(18)
|
||||
#define SCTLR_nTWI BIT(16)
|
||||
#define SCTLR_UCT BIT(15)
|
||||
#define SCTLR_DZE BIT(14)
|
||||
#define SCTLR_EnDB BIT(13)
|
||||
#define SCTLR_I BIT(12)
|
||||
#define SCTLR_EOS BIT(11)
|
||||
#define SCTLR_EnRCTX BIT(10)
|
||||
#define SCTLR_UMA BIT(9)
|
||||
#define SCTLR_SED BIT(8)
|
||||
#define SCTLR_ITD BIT(7)
|
||||
#define SCTLR_nAA BIT(6)
|
||||
#define SCTLR_CP15BEN BIT(5)
|
||||
#define SCTLR_SA0 BIT(4)
|
||||
#define SCTLR_SA BIT(3)
|
||||
#define SCTLR_C BIT(2)
|
||||
#define SCTLR_A BIT(1)
|
||||
#define SCTLR_M BIT(0)
|
||||
|
||||
#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
|
||||
#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
|
||||
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
|
||||
|
|
@ -173,6 +221,57 @@
|
|||
#define SPSR_F BIT(6)
|
||||
#define SPSR_M GENMASK(4, 0)
|
||||
|
||||
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
|
||||
#define TCR_DS BIT(59)
|
||||
#define TCR_TCMA1 BIT(58)
|
||||
#define TCR_TCMA0 BIT(57)
|
||||
#define TCR_E0PD1 BIT(56)
|
||||
#define TCR_E0PD0 BIT(55)
|
||||
#define TCR_NFD1 BIT(54)
|
||||
#define TCR_NFD0 BIT(53)
|
||||
#define TCR_TBID1 BIT(52)
|
||||
#define TCR_TBID0 BIT(51)
|
||||
#define TCR_HWU162 BIT(50)
|
||||
#define TCR_HWU161 BIT(49)
|
||||
#define TCR_HWU160 BIT(48)
|
||||
#define TCR_HWU159 BIT(47)
|
||||
#define TCR_HWU062 BIT(46)
|
||||
#define TCR_HWU061 BIT(45)
|
||||
#define TCR_HWU060 BIT(44)
|
||||
#define TCR_HWU059 BIT(43)
|
||||
#define TCR_HPD1 BIT(42)
|
||||
#define TCR_HPD0 BIT(41)
|
||||
#define TCR_HD BIT(40)
|
||||
#define TCR_HA BIT(39)
|
||||
#define TCR_TBI1 BIT(38)
|
||||
#define TCR_TBI0 BIT(37)
|
||||
#define TCR_AS BIT(36)
|
||||
#define TCR_IPS GENMASK(34, 32)
|
||||
#define TCR_IPS_1TB 0b010UL
|
||||
#define TCR_TG1 GENMASK(31, 30)
|
||||
#define TCR_TG1_16K 0b01UL
|
||||
#define TCR_SH1 GENMASK(29, 28)
|
||||
#define TCR_SH1_IS 0b11UL
|
||||
#define TCR_ORGN1 GENMASK(27, 26)
|
||||
#define TCR_ORGN1_WBWA 0b01UL
|
||||
#define TCR_IRGN1 GENMASK(25, 24)
|
||||
#define TCR_IRGN1_WBWA 0b01UL
|
||||
#define TCR_EPD1 BIT(23)
|
||||
#define TCR_A1 BIT(22)
|
||||
#define TCR_T1SZ GENMASK(21, 16)
|
||||
#define TCR_T1SZ_48BIT 16UL
|
||||
#define TCR_TG0 GENMASK(15, 14)
|
||||
#define TCR_TG0_16K 0b10UL
|
||||
#define TCR_SH0 GENMASK(13, 12)
|
||||
#define TCR_SH0_IS 0b11UL
|
||||
#define TCR_ORGN0 GENMASK(11, 10)
|
||||
#define TCR_ORGN0_WBWA 0b01UL
|
||||
#define TCR_IRGN0 GENMASK(9, 8)
|
||||
#define TCR_IRGN0_WBWA 0b01UL
|
||||
#define TCR_EPD0 BIT(7)
|
||||
#define TCR_T0SZ GENMASK(5, 0)
|
||||
#define TCR_T0SZ_48BIT 16UL
|
||||
|
||||
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
|
||||
// Profile(A)
|
||||
#define VTCR_SL2 BIT(33)
|
||||
|
|
|
|||
46
src/memory.c
46
src/memory.c
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: MIT */
|
||||
|
||||
#include "memory.h"
|
||||
#include "cpu_regs.h"
|
||||
#include "fb.h"
|
||||
#include "utils.h"
|
||||
|
||||
|
|
@ -61,41 +62,6 @@ static inline void write_sctlr(u64 val)
|
|||
#define PERM_RW PTE_PXN | PTE_UXN
|
||||
#define PERM_RWX 0
|
||||
|
||||
/*
|
||||
* https://developer.arm.com/docs/ddi0595/g/aarch64-system-registers/sctlr_el1
|
||||
* SCTLR_SPAN disables PAN getting enabled on exceptions.
|
||||
* SCTLR_I enables instruction caches.
|
||||
* SCTLR_C enables data caches.
|
||||
* SCTLR_M enables the MMU.
|
||||
*/
|
||||
#define SCTLR_SPAN BIT(23)
|
||||
#define SCTLR_I BIT(12)
|
||||
#define SCTLR_C BIT(2)
|
||||
#define SCTLR_M BIT(0)
|
||||
|
||||
/*
|
||||
* https://developer.arm.com/docs/ddi0595/h/aarch64-system-registers/tcr_el1
|
||||
* TCR_IPS_1TB selects 40 bits/1TB intermediate physical address size
|
||||
* TCR_PS_1TB selects 40 bits/1TB physical address size
|
||||
* TCR_TG0_16K selects 16K pages
|
||||
* TCR_SH0_IS marks memory used during translation table walks as inner sharable
|
||||
* TCR_ORGN0_WBWA and TCR_IRGN0_WBWA set the cacheability atrributes for memory
|
||||
* used during translation table walks to Inner/Outer
|
||||
* Write-Back Read-Allocate Write-Allocate Cacheable
|
||||
* TCR_T0SZ_48BIT selects 48bit virtual addresses
|
||||
*/
|
||||
#define TCR_IPS_1TB ((0b010UL) << 32)
|
||||
#define TCR_TG1_16K ((0b01UL) << 30)
|
||||
#define TCR_SH1_IS ((0b11UL) << 28)
|
||||
#define TCR_ORGN1_WBWA ((0b01UL) << 26)
|
||||
#define TCR_IRGN1_WBWA ((0b01UL) << 24)
|
||||
#define TCR_T1SZ_48BIT ((16UL) << 16)
|
||||
#define TCR_TG0_16K ((0b10UL) << 14)
|
||||
#define TCR_SH0_IS ((0b11UL) << 12)
|
||||
#define TCR_ORGN0_WBWA ((0b01UL) << 10)
|
||||
#define TCR_IRGN0_WBWA ((0b01UL) << 8)
|
||||
#define TCR_T0SZ_48BIT ((16UL) << 0)
|
||||
|
||||
/*
|
||||
* aarch64 allows to configure attribute sets for up to eight different memory
|
||||
* types. we need normal memory and two types of device memory (nGnRnE and
|
||||
|
|
@ -310,9 +276,13 @@ static void mmu_configure(void)
|
|||
msr(MAIR_EL1, (MAIR_ATTR_NORMAL_DEFAULT << MAIR_SHIFT_NORMAL) |
|
||||
(MAIR_ATTR_DEVICE_nGnRnE << MAIR_SHIFT_DEVICE_nGnRnE) |
|
||||
(MAIR_ATTR_DEVICE_nGnRE << MAIR_SHIFT_DEVICE_nGnRE));
|
||||
msr(TCR_EL1, TCR_IPS_1TB | TCR_TG1_16K | TCR_SH1_IS | TCR_ORGN1_WBWA | TCR_IRGN1_WBWA |
|
||||
TCR_T1SZ_48BIT | TCR_TG0_16K | TCR_SH0_IS | TCR_ORGN0_WBWA | TCR_IRGN0_WBWA |
|
||||
TCR_T0SZ_48BIT);
|
||||
msr(TCR_EL1, FIELD_PREP(TCR_IPS, TCR_IPS_1TB) | FIELD_PREP(TCR_TG1, TCR_TG1_16K) |
|
||||
FIELD_PREP(TCR_SH1, TCR_SH1_IS) | FIELD_PREP(TCR_ORGN1, TCR_ORGN1_WBWA) |
|
||||
FIELD_PREP(TCR_IRGN1, TCR_IRGN1_WBWA) | FIELD_PREP(TCR_T1SZ, TCR_T1SZ_48BIT) |
|
||||
FIELD_PREP(TCR_TG0, TCR_TG0_16K) | FIELD_PREP(TCR_SH0, TCR_SH0_IS) |
|
||||
FIELD_PREP(TCR_ORGN0, TCR_ORGN0_WBWA) | FIELD_PREP(TCR_IRGN0, TCR_IRGN0_WBWA) |
|
||||
FIELD_PREP(TCR_T0SZ, TCR_T0SZ_48BIT));
|
||||
|
||||
msr(TTBR0_EL1, (uintptr_t)pagetable_L0);
|
||||
msr(TTBR1_EL1, (uintptr_t)pagetable_L0);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue