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https://github.com/AsahiLinux/m1n1
synced 2024-11-22 06:33:03 +00:00
hv: Implement basic exception handling
Allows Python to handle hypervisor exceptions, and implements exception info display and basic debug commands. Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
parent
b015dcf272
commit
4d64c33ca6
10 changed files with 269 additions and 5 deletions
2
Makefile
2
Makefile
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@ -43,7 +43,7 @@ OBJECTS := \
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exception.o exception_asm.o \
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fb.o font.o font_retina.o \
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heapblock.o \
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hv.o hv_vm.o \
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hv.o hv_vm.o hv_exc.o hv_asm.o \
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iodev.o \
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kboot.o \
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main.o \
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@ -1,11 +1,14 @@
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#!/usr/bin/env python3
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# SPDX-License-Identifier: MIT
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import sys
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from tgtypes import *
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from proxy import IODEV
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from proxy import IODEV, START, EXC, EXC_RET, ExcInfo
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from utils import *
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from sysreg import *
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from macho import MachO
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import shell
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class HV:
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PTE_VALID = 1 << 0
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@ -34,12 +37,49 @@ class HV:
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def map_sw(self, ipa, pa, size):
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assert self.p.hv_map(ipa, pa | self.SPTE_MAP, size, 1) >= 0
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def handle_exception(self, reason, code, info):
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self.ctx = ctx = ExcInfo.parse(self.iface.readmem(info, ExcInfo.sizeof()))
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print(f"Guest exception: {code.name}")
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self.u.print_exception(code, ctx)
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locals = {
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"hv": self,
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"iface": self.iface,
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"p": self.p,
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"u": self.u,
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}
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for attr in dir(self):
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locals[attr] = getattr(self, attr)
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shell.run_shell(locals, "Entering debug shell", "Returning from exception")
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self.iface.writemem(info, ExcInfo.build(self.ctx))
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self.p.exit(EXC_RET.HANDLED)
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def skip(self):
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self.ctx.elr += 4
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raise shell.ExitConsole()
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def cont(self):
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raise shell.ExitConsole()
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def exit(self):
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sys.exit(0)
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def init(self):
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self.iodev = self.p.iodev_whoami()
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print("Initializing hypervisor over iodev %s" % self.iodev)
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self.p.hv_init()
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self.iface.set_handler(START.EXCEPTION_LOWER, EXC.SYNC, self.handle_exception)
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self.iface.set_handler(START.EXCEPTION_LOWER, EXC.IRQ, self.handle_exception)
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self.iface.set_handler(START.EXCEPTION_LOWER, EXC.FIQ, self.handle_exception)
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self.iface.set_handler(START.EXCEPTION_LOWER, EXC.SERROR, self.handle_exception)
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self.map_hw(0x2_00000000, 0x2_00000000, 0x5_00000000)
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self.map_hw(0x8_00000000, 0x8_00000000, 0x4_00000000)
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@ -117,5 +157,7 @@ class HV:
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print(f"Jumping to entrypoint at 0x{self.entry:x}")
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self.p.reboot(self.entry, self.guest_base + self.bootargs_off, el1=True)
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self.iface.ttymode()
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self.iface.dev.timeout = None
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# Does not return
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self.p.hv_start(self.entry, self.guest_base + self.bootargs_off)
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@ -470,6 +470,7 @@ class M1N1Proxy:
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P_HV_INIT = 0xc00
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P_HV_MAP = 0xc01
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P_HV_START = 0xc02
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def __init__(self, iface, debug=False):
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self.debug = debug
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@ -792,6 +793,9 @@ class M1N1Proxy:
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return self.request(self.P_HV_INIT)
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def hv_map(self, from_, to, size, incr):
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return self.request(self.P_HV_MAP, from_, to, size, incr)
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def hv_start(self, entry, *args):
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# does not return
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return self.request(self.P_HV_START, entry, *args)
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if __name__ == "__main__":
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import serial
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@ -129,6 +129,32 @@ class ProxyUtils(object):
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print(f"Pushing ADT ({adt_size} bytes)...")
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self.iface.writemem(adt_base, self.adt_data)
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def print_exception(self, code, ctx):
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print(f" SPSR = {ctx.spsr}")
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print(f" ELR = 0x{ctx.elr:x}")
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print(f" ESR = {ctx.esr}")
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print(f" FAR = 0x{ctx.far:x}")
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for i in range(0, 31, 4):
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j = min(30, i + 3)
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print(f" {f'x{i}-x{j}':>7} = {' '.join(f'{r:016x}' for r in ctx.regs[i:j + 1])}")
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if ctx.esr.EC == ESR_EC.MSR:
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print()
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print(" == MSR fault decoding ==")
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iss = ESR_ISS_MSR(ctx.esr.ISS)
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enc = iss.Op0, iss.Op1, iss.CRn, iss.CRm, iss.Op2
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if enc in sysreg_rev:
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name = sysreg_rev[enc]
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else:
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name = f"s{iss.Op0}_{iss.Op1}_c{iss.CRn}_c{iss.CRm}_{iss.op2}"
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if iss.DIR == MSR_DIR.READ:
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print(f" Instruction: mrs x{iss.Rt}, {name}")
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else:
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print(f" Instruction: msr x{iss.Rt}, {name}")
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print()
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class LazyADT:
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def __init__(self, utils):
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self.__dict__["_utils"] = utils
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@ -22,6 +22,8 @@ extern volatile int exc_count;
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void exception_initialize(void);
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void exception_shutdown(void);
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void print_regs(u64 *regs, int el12);
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uint64_t el0_call(void *func, uint64_t a, uint64_t b, uint64_t c, uint64_t d);
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uint64_t el1_call(void *func, uint64_t a, uint64_t b, uint64_t c, uint64_t d);
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14
src/hv.c
14
src/hv.c
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@ -4,6 +4,10 @@
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#include "assert.h"
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#include "cpu_regs.h"
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void hv_enter_guest(u64 x0, u64 x1, u64 x2, u64 x3, void *entry) __attribute__((noreturn));
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extern char _hv_vectors_start[0];
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void hv_init(void)
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{
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// Enable physical timer for EL1
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@ -20,8 +24,18 @@ void hv_init(void)
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HCR_AMO | // Trap SError exceptions
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HCR_VM); // Enable stage 2 translation
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// No guest vectors initially
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msr(VBAR_EL12, 0);
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sysop("dsb ishst");
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sysop("tlbi alle1is");
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sysop("dsb ish");
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sysop("isb");
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}
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void hv_start(void *entry, u64 regs[4])
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{
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msr(VBAR_EL1, _hv_vectors_start);
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hv_enter_guest(regs[0], regs[1], regs[2], regs[3], entry);
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}
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98
src/hv_asm.S
Normal file
98
src/hv_asm.S
Normal file
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@ -0,0 +1,98 @@
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/* spDx-License-Identifier: MIT */
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.align 11
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.globl _hv_vectors_start
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_hv_vectors_start:
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mov x9, '0'
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b cpu_reset
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.align 7
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mov x9, '1'
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b exc_unk
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.align 7
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mov x9, '2'
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b exc_unk
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.align 7
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mov x9, '3'
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b exc_unk
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.align 7
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b _v_sp0_sync
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.align 7
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b _v_sp0_irq
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.align 7
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b _v_sp0_fiq
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.align 7
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b _v_sp0_serr
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.align 7
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b _v_hv_sync
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.align 7
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b _v_hv_irq
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.align 7
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b _v_hv_fiq
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.align 7
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b _v_hv_serr
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.align 7
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mov x9, 'p'
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b exc_unk
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.align 7
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mov x9, 'q'
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b exc_unk
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.align 7
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mov x9, 'r'
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b exc_unk
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.align 7
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mov x9, 's'
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b exc_unk
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.align 7
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.globl _v_hv_sync
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.type _v_hv_sync, @function
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_v_hv_sync:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl hv_exc_sync
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b _exc_return
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.globl _v_hv_irq
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.type _v_hv_irq, @function
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_v_hv_irq:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl hv_exc_irq
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b _exc_return
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.globl _v_hv_fiq
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.type _v_hv_fiq, @function
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_v_hv_fiq:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl hv_exc_fiq
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b _exc_return
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.globl _v_hv_serr
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.type _v_hv_serr, @function
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_v_hv_serr:
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str x30, [sp, #-16]!
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bl _exc_entry
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bl hv_exc_serr
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b _exc_return
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.globl hv_enter_guest
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.type hv_enter_guest, @function
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hv_enter_guest:
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mrs x5, daif
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msr daifclr, 3
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mov x6, #5
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orr x5, x5, x6 // EL1h
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msr spsr_el2, x5
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msr elr_el2, x4
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msr spsel, #0
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mov x5, #0
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mov sp, x5
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eret
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74
src/hv_exc.c
Normal file
74
src/hv_exc.c
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/* SPDX-License-Identifier: MIT */
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#include "hv.h"
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#include "assert.h"
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#include "cpu_regs.h"
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#include "exception.h"
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#include "string.h"
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#include "uartproxy.h"
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static void hv_exc_proxy(u64 *regs, uartproxy_exc_code_t type)
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{
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struct uartproxy_exc_info exc_info = {
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.spsr = mrs(SPSR_EL2),
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.elr = mrs(ELR_EL2),
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.esr = mrs(ESR_EL2),
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.far = mrs(FAR_EL2),
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.sp = {mrs(SP_EL0), mrs(SP_EL1), 0},
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.mpidr = mrs(MPIDR_EL1),
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};
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memcpy(exc_info.regs, regs, sizeof(exc_info.regs));
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struct uartproxy_msg_start start = {
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.reason = START_EXCEPTION_LOWER,
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.code = type,
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.info = &exc_info,
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};
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int ret = uartproxy_run(&start);
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if (ret == EXC_RET_HANDLED) {
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memcpy(regs, exc_info.regs, sizeof(exc_info.regs));
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msr(SPSR_EL2, exc_info.spsr);
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msr(ELR_EL2, exc_info.elr);
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msr(SP_EL0, exc_info.sp[0]);
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msr(SP_EL1, exc_info.sp[1]);
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return;
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}
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printf("Guest exception not handled, rebooting.\n");
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print_regs(regs, 0);
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reboot();
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}
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void hv_exc_sync(u64 *regs)
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{
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#if 0
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u64 esr = mrs(ESR_EL2);
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u32 ec = FIELD_GET(ESR_EC, esr);
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switch (ec) {
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case ESR_EC_DABORT_LOWER:
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if (handle_dabort(regs))
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return;
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break;
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}
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#endif
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hv_exc_proxy(regs, EXC_SYNC);
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}
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void hv_exc_irq(u64 *regs)
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{
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hv_exc_proxy(regs, EXC_IRQ);
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}
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void hv_exc_fiq(u64 *regs)
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{
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hv_exc_proxy(regs, EXC_FIQ);
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}
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void hv_exc_serr(u64 *regs)
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{
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hv_exc_proxy(regs, EXC_SERROR);
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}
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@ -387,6 +387,9 @@ int proxy_process(ProxyRequest *request, ProxyReply *reply)
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case P_HV_MAP:
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hv_map(request->args[0], request->args[1], request->args[2], request->args[3]);
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break;
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case P_HV_START:
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hv_start((void *)request->args[0], &request->args[1]);
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break;
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default:
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reply->status = S_BADCMD;
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@ -105,7 +105,8 @@ typedef enum {
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P_DART_UNMAP,
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P_HV_INIT = 0xc00,
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P_HV_MAP = 0xc01,
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P_HV_MAP,
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P_HV_START,
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} ProxyOp;
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