This stops DCP from killing our modeset if the connection cycles.
Also force a (potential) configure cycle if the display is external;
this makes sure updated stage2s will have a chance at fixing issues of
old stage1s. Modesetting is fast when it's the same mode as before.
Signed-off-by: Hector Martin <marcan@marcan.st>
Get rid of the hv_rearm() thing (which was always a bit dodgy) and
instead properly make sure that all CPUs rendezvous when needed and
switch the active proxy thread without ever exiting exception context.
The Python side can now switch proxy context (by waiting directly for
a proxy boot) without having to exit out of the hypervisor callback,
so cpu() now works as a normal Python method.
Add a cpus() iterator so you can do things like:
>>> for i in cpus(): bt()
Signed-off-by: Hector Martin <marcan@marcan.st>
The HV tick polling now only runs on CPU#0. All CPUs have the 1000Hz
HV tick, but secondaries only use it to poll the FIQ state and that path
does not take the BHL if no other FIQ was pending.
Signed-off-by: Hector Martin <marcan@marcan.st>
Also capture config at cpu0 guest entry time, to make sure we don't
carry over guest changes to EL1 regs after that.
Signed-off-by: Hector Martin <marcan@marcan.st>
This does an explicit hypervisor rendezvous. It's not great because it
introduces spurious guest IPIs, but xnu doesn't seem to care...
Signed-off-by: Hector Martin <marcan@marcan.st>
This works to get to a serial shell on Linux, and to use m1n1-as-LV1
proxyclient with M1N1DEVICE=/dev/m1n1-sec
Signed-off-by: Hector Martin <marcan@marcan.st>
Restore the interrupt masks on chainload or HV guest start. The
interrupt mask is not restored on the USB-C port used by the hypervisor.
This prevents an interrupt storm in the guest when the other USB-C port
is exposed to the guest. Both tps6598x share unfortunately an interrupt
line.
Signed-off-by: Janne Grunau <j@jannau.net>
Allows Python to handle hypervisor exceptions, and implements exception
info display and basic debug commands.
Signed-off-by: Hector Martin <marcan@marcan.st>
