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m1n1.trace.i2c: Clean up handling of page/immediate split

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Also fix detection of read being a read of the page control register.

Signed-off-by: Martin Povišer <povik@protonmail.com>
This commit is contained in:
Martin Povišer 2022-06-14 20:24:42 +02:00 • committed by Hector Martin
parent 56d8de66db
commit e2065decbe
1 changed files with 11 additions and 7 deletions
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18
proxyclient/m1n1/trace/i2c.py
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@ -171,20 +171,24 @@ class I2CRegMapTracer(I2CDevTracer):
self.regbytes.append(data) self.regbytes.append(data)
if len(self.regbytes)*8 >= self.pageshift: if len(self.regbytes)*8 >= self.pageshift:
subreg = int.from_bytes(bytes(self.regbytes), immediate = int.from_bytes(bytes(self.regbytes),
byteorder="big") byteorder="big")
self.reg = self.page << self.pageshift | subreg self.reg = self.page << self.pageshift | immediate
return True return True
@property
def reg_imm(self):
'''Returns the 'immediate' part of current register address'''
return self.reg & ~(~0 << self.pageshift)
def handle_page_register(self, data): def handle_page_register(self, data):
if not self.paged: if not self.paged:
return False return False
subreg = self.reg & ~(~0 << self.pageshift) if self.reg_imm >= self.npagebytes:
if subreg >= self.npagebytes:
return False return False
shift = 8 * subreg shift = 8 * self.reg_imm
self.page &= ~(0xff << shift) self.page &= ~(0xff << shift)
self.page |= data << shift self.page |= data << shift
return True return True
@ -192,7 +196,7 @@ class I2CRegMapTracer(I2CDevTracer):
def write(self, data): def write(self, data):
if self.handle_addressing(data): if self.handle_addressing(data):
return return
if self.handle_page_register(data): elif self.handle_page_register(data):
pass pass
else: else:
self.regwrite(self.reg, data) self.regwrite(self.reg, data)
@ -201,7 +205,7 @@ class I2CRegMapTracer(I2CDevTracer):
super().write(data) super().write(data)
def read(self, data): def read(self, data):
if self.reg & 0xff != 0: if self.reg_imm >= self.npagebytes:
self.regread(self.reg, data) self.regread(self.reg, data)
self.reg += 1 self.reg += 1
super().read(data) super().read(data)