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https://github.com/AsahiLinux/m1n1
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m1n1.hw.codecs.cs42l84: File the ohmmeter codec regmap
Move the regmap from experiments/ to a handier place. Also add the codec to trace_codecs.py and codecshell.py. Signed-off-by: Martin Povišer <povik@protonmail.com>
This commit is contained in:
Martin Povišer
Hector Martin
parent
0da13afda8
commit
56d8de66db
5 changed files with 229 additions and 219 deletions
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@ -4,227 +4,12 @@ import sys, pathlib
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import time
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sys.path.append(str(pathlib.Path(__file__).resolve().parents[1]))
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from m1n1.utils import *
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from enum import IntEnum
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from m1n1.setup import *
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from m1n1.hw.i2c import I2C, I2CRegMapDev
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class R_IRQ_MASK1(Register8):
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RING_PLUG = 0
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RING_UNPLUG = 1
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class E_DCID_GND_SEL(IntEnum):
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NONE = 0
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HS3 = 1
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HS4 = 2
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class E_DCID_Z_RANGE(IntEnum):
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NONE = 0
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UNK2 = 2
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UNK3 = 3
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class R_DCID_CTRL1(Register8):
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Z_RANGE = 2, 0, E_DCID_Z_RANGE
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class R_DCID_CTRL2(Register8):
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GND_SEL = 6, 4, E_DCID_GND_SEL
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class R_DCID_CTRL3(Register8):
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START = 0
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class R_DCID_STATUS(Register32):
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OVERALL = 9, 0
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DONE = 10
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U = 20, 11
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D = 30, 21
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class E_DEBOUNCE_TIME(IntEnum):
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T_0MS = 0b000
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T_125MS = 0b001
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T_250MS = 0b010
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T_500MS = 0b011
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T_750MS = 0b100
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T_1S = 0b101
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class R_TR_SENSE_CTRL(Register8):
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INV = 7
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UNK1 = 6
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FALLTIME = 5, 3, E_DEBOUNCE_TIME
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RISETIME = 2, 0, E_DEBOUNCE_TIME
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class R_TR_SENSE_STATUS(Register8):
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RING_PLUG = 0
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RING_UNPLUG = 1
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class R_MSM_BLOCK_EN3(Register8):
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TR_SENSE_EN = 3
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DCID_EN = 4
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class R_HS_CLAMP_DISABLE(Register8):
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HS_CLAMP_DISABLE = 0
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class E_SAMP_RATE(IntEnum):
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S_16KHZ = 1
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S_24KHZ = 2
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S_32KHZ = 3
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S_48KHZ = 4
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S_96KHZ = 5
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S_192KHZ = 6
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S_22K05HZ = 10
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S_44K1HZ = 12
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S_88K2HZ = 13
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S_176K4HZ = 14
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class R_CCM_SAMP_RATE(Register8):
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RATE = 7, 0, E_SAMP_RATE
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class R_DAC_CTRL1(Register8):
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HP_LOAD = 2 # maybe
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UNK2 = 4
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UNK3 = 5 # always set
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HIGH_V = 6
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class E_PULLDOWN_R(IntEnum):
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NONE = 0x0
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R_UNK8 = 0x8
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R_1K1OHMS = 0xc
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class R_DAC_CTRL2(Register8):
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PULLDOWN_R = 3, 0, E_PULLDOWN_R
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class R_HSBIAS_SC_AUTOCTL(Register8):
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TIP_SENSE_EN = 5
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class E_TIP_SENSE_CTRL(IntEnum):
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DISABLED = 0b00
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DIG_INPUT = 0b01
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SHORT_DET = 0b11
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class R_TIP_SENSE_CTRL2(Register8):
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CTRL = 7, 6, E_TIP_SENSE_CTRL
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INV = 5
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class E_HSBIAS_CTRL(IntEnum):
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HI_Z = 0b00
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U_0V0 = 0b01
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U_2V0 = 0b10
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U_2V7 = 0b11
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class R_MISC_DET_CTRL(Register8):
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HSBIAS_CTRL = 2, 1, E_HSBIAS_CTRL
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class E_S0_DEBOUNCE_TIME(IntEnum):
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T_10MS = 0b000
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T_20MS = 0b001
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T_30MS = 0b010
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T_40MS = 0b011
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T_50MS = 0b100
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T_60MS = 0b101
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T_70MS = 0b110
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T_80MS = 0b111
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class R_MIC_DET_CTRL2(Register8):
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DEBOUNCE_TIME = 7, 5, E_S0_DEBOUNCE_TIME
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class R_MIC_DET_CTRL4(Register8):
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LATCH_TO_VP = 1
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class R_HS_SWITCH_CTRL(Register8):
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REF_HS3 = 7
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REF_HS4 = 6
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HSB_FILT_HS3 = 5
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HSB_FILT_HS4 = 4
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HSB_HS3 = 3
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HSB_HS4 = 2
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GNDHS_HS3 = 1
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GNDHS_HS4 = 0
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class CS42L84Registers(RegMap):
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DEVID = irange(0x0, 5), Register8
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FREEZE = 0x6, Register8
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SW_RESET = 0x203, Register8
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IRQ_STATUS = irange(0x400, 3), Register8
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IRQ_MASK1 = 0x418, R_IRQ_MASK1
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IRQ_MASK2 = 0x419, Register8
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IRQ_MASK3 = 0x41a, Register8
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CCM_CTRL = irange(0x600, 4), Register8
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CCM_SAMP_RATE = 0x601, R_CCM_SAMP_RATE
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CCM_ASP_CLK_CTRL = 0x608, Register8
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PLL_CTRL = 0x800, Register8
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PLL_DIV_FRAC = irange(0x804, 3), Register8
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PLL_DIV_INT = 0x807, Register8
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PLL_DIVOUT = 0x808, Register8
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DCID_CTRL1 = 0x1200, R_DCID_CTRL1
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DCID_CTRL2 = 0x1201, R_DCID_CTRL2
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DCID_CTRL3 = 0x1202, R_DCID_CTRL3
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DCID_TRIM_OFFSET = 0x1207, Register8
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DCID_TRIM_SLOPE = 0x120a, Register8
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# R_pull = 1100 - (regval - 128)*2
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DCID_PULLDOWN_TRIM = 0x120b, Register8
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DCID_STATUS = 0x120c, R_DCID_STATUS
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# tip/ring sense
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TR_SENSE_CTRL1 = 0x1280, Register8
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TR_SENSE_CTRL2 = 0x1281, Register8
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RING_SENSE_CTRL = 0x1282, R_TR_SENSE_CTRL
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TIP_SENSE_CTRL = 0x1283, R_TR_SENSE_CTRL
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TR_SENSE_STATUS = 0x1288, R_TR_SENSE_STATUS
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HSBIAS_SC_AUTOCTL = 0x1470, R_HSBIAS_SC_AUTOCTL
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WAKE_CTRL = 0x1471, Register8 # guess (cs42l42)
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TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2 # guess (cs42l42)
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MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL # guess (cs42l42)
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MIC_DET_CTRL2 = 0x1478, R_MIC_DET_CTRL2
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MIC_DET_CTRL4 = 0x1477, R_MIC_DET_CTRL4
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MIKEY_DET_STATUS = irange(0x147c, 2), Register8
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MIKEY_DET_IRQ_MASK = irange(0x1480, 2), Register8
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MIKEY_DET_IRQ_STATUS = irange(0x1484, 2), Register8
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MSM_BLOCK_EN3 = 0x1802, R_MSM_BLOCK_EN3
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HS_SWITCH_CTRL = 0x1812, R_HS_SWITCH_CTRL
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HS_CLAMP_DISABLE = 0x1813, R_HS_CLAMP_DISABLE
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ADC_CTRL = irange(0x2000, 4), Register8
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DAC_CTRL1 = 0x3000, R_DAC_CTRL1
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DAC_CTRL2 = 0x3001, R_DAC_CTRL2
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DACA_VOL_LSB = 0x3004, Register8
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DACA_VOL_MSB = 0x3005, Register8 # sign bit
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DACB_VOL_LSB = 0x3006, Register8
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DACB_VOL_MSB = 0x3007, Register8 # sign bit
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HP_VOL_CTRL = 0x3020, Register8
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HP_CLAMP_CTRL = 0x3123, Register8
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ASP_CTRL = 0x5000, Register8
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ASP_FSYNC_CTRL = irange(0x500f, 3), Register8
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ASP_DATA_CTRL = 0x5018, Register8
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ASP_RX_EN = 0x5020, Register8
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ASP_TX_EN = 0x5024, Register8
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ASP_RXSLOT_CH1_LSB = 0x5028, Register8
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ASP_RXSLOT_CH1_MSB = 0x5029, Register8
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ASP_RXSLOT_CH2_LSB = 0x502c, Register8
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ASP_RXSLOT_CH2_MSB = 0x502d, Register8
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ASP_TXSLOT_CH1_LSB = 0x5068, Register8
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ASP_TXSLOT_CH1_MSB = 0x5068, Register8
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from m1n1.hw.codecs.cs42l84 import *
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class CS42L84(I2CRegMapDev):
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REGMAP = CS42L84Registers
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REGMAP = CS42L84Regs
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ADDRESSING = (0, 2)
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def read_devid():
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@ -12,6 +12,10 @@ class TAS5770Tracer(I2CRegMapTracer):
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REGMAP = TAS5770Regs
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ADDRESSING = (1, 1)
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class CS42L84Tracer(I2CRegMapTracer):
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REGMAP = CS42L84Regs
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ADDRESSING = (0, 2)
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i2c_tracers = {}
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for node in hv.adt["/arm-io"]:
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@ -27,7 +31,8 @@ for node in hv.adt["/arm-io"]:
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dcls = {
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"audio-control,tas5770": TAS5770Tracer,
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"audio-control,sn012776": SN012776Tracer
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"audio-control,sn012776": SN012776Tracer,
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"audio-control,cs42l84": CS42L84Tracer,
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}.get(devnode.compatible[0], None)
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if dcls:
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bus.add_device(
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@ -1,5 +1,6 @@
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from m1n1.utils import RegMap, Register8
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from enum import IntEnum
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from .cs42l84 import *
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class E_PWR_MODE(IntEnum):
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ACTIVE = 0
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214
proxyclient/m1n1/hw/codecs/cs42l84.py
Normal file
214
proxyclient/m1n1/hw/codecs/cs42l84.py
Normal file
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@ -0,0 +1,214 @@
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from m1n1.utils import Register8, Register32, RegMap, irange
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from enum import IntEnum
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class R_IRQ_MASK1(Register8):
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RING_PLUG = 0
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RING_UNPLUG = 1
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class E_DCID_GND_SEL(IntEnum):
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NONE = 0
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HS3 = 1
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HS4 = 2
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class E_DCID_Z_RANGE(IntEnum):
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NONE = 0
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UNK2 = 2
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UNK3 = 3
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class R_DCID_CTRL1(Register8):
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Z_RANGE = 2, 0, E_DCID_Z_RANGE
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class R_DCID_CTRL2(Register8):
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GND_SEL = 6, 4, E_DCID_GND_SEL
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class R_DCID_CTRL3(Register8):
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START = 0
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class R_DCID_STATUS(Register32):
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OVERALL = 9, 0
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DONE = 10
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U = 20, 11
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D = 30, 21
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class E_DEBOUNCE_TIME(IntEnum):
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T_0MS = 0b000
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T_125MS = 0b001
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T_250MS = 0b010
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T_500MS = 0b011
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T_750MS = 0b100
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T_1S = 0b101
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class R_TR_SENSE_CTRL(Register8):
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INV = 7
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UNK1 = 6
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FALLTIME = 5, 3, E_DEBOUNCE_TIME
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RISETIME = 2, 0, E_DEBOUNCE_TIME
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class R_TR_SENSE_STATUS(Register8):
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RING_PLUG = 0
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RING_UNPLUG = 1
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TIP_PLUG = 2
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TIP_UNPLUG = 3
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class R_MSM_BLOCK_EN3(Register8):
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TR_SENSE_EN = 3
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DCID_EN = 4
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class R_HS_CLAMP_DISABLE(Register8):
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HS_CLAMP_DISABLE = 0
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class E_SAMP_RATE(IntEnum):
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S_16KHZ = 1
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S_24KHZ = 2
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S_32KHZ = 3
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S_48KHZ = 4
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S_96KHZ = 5
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S_192KHZ = 6
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S_22K05HZ = 10
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S_44K1HZ = 12
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S_88K2HZ = 13
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S_176K4HZ = 14
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class R_CCM_SAMP_RATE(Register8):
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RATE = 7, 0, E_SAMP_RATE
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class R_DAC_CTRL1(Register8):
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HP_LOAD = 2 # maybe
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UNK2 = 4
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UNK3 = 5 # always set
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HIGH_V = 6
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class E_PULLDOWN_R(IntEnum):
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NONE = 0x0
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R_UNK8 = 0x8
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R_1K1OHMS = 0xc
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class R_DAC_CTRL2(Register8):
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PULLDOWN_R = 3, 0, E_PULLDOWN_R
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class R_HSBIAS_SC_AUTOCTL(Register8):
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TIP_SENSE_EN = 5
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class E_TIP_SENSE_CTRL(IntEnum):
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DISABLED = 0b00
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DIG_INPUT = 0b01
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SHORT_DET = 0b11
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class R_TIP_SENSE_CTRL2(Register8):
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CTRL = 7, 6, E_TIP_SENSE_CTRL
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INV = 5
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class E_HSBIAS_CTRL(IntEnum):
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HI_Z = 0b00
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U_0V0 = 0b01
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U_2V0 = 0b10
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U_2V7 = 0b11
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class R_MISC_DET_CTRL(Register8):
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HSBIAS_CTRL = 2, 1, E_HSBIAS_CTRL
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class E_S0_DEBOUNCE_TIME(IntEnum):
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T_10MS = 0b000
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T_20MS = 0b001
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T_30MS = 0b010
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T_40MS = 0b011
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T_50MS = 0b100
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T_60MS = 0b101
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T_70MS = 0b110
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T_80MS = 0b111
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class R_MIC_DET_CTRL2(Register8):
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DEBOUNCE_TIME = 7, 5, E_S0_DEBOUNCE_TIME
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class R_MIC_DET_CTRL4(Register8):
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LATCH_TO_VP = 1
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class R_HS_SWITCH_CTRL(Register8):
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REF_HS3 = 7
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REF_HS4 = 6
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HSB_FILT_HS3 = 5
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HSB_FILT_HS4 = 4
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HSB_HS3 = 3
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HSB_HS4 = 2
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GNDHS_HS3 = 1
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GNDHS_HS4 = 0
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class CS42L84Regs(RegMap):
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DEVID = irange(0x0, 5), Register8
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FREEZE = 0x6, Register8
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SW_RESET = 0x203, Register8
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IRQ_STATUS = irange(0x400, 3), Register8
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IRQ_MASK1 = 0x418, R_IRQ_MASK1
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IRQ_MASK2 = 0x419, Register8
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IRQ_MASK3 = 0x41a, Register8
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CCM_CTRL = irange(0x600, 4), Register8
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CCM_SAMP_RATE = 0x601, R_CCM_SAMP_RATE
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CCM_ASP_CLK_CTRL = 0x608, Register8
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PLL_CTRL = 0x800, Register8
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PLL_DIV_FRAC = irange(0x804, 3), Register8
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PLL_DIV_INT = 0x807, Register8
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PLL_DIVOUT = 0x808, Register8
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DCID_CTRL1 = 0x1200, R_DCID_CTRL1
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DCID_CTRL2 = 0x1201, R_DCID_CTRL2
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DCID_CTRL3 = 0x1202, R_DCID_CTRL3
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DCID_TRIM_OFFSET = 0x1207, Register8
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DCID_TRIM_SLOPE = 0x120a, Register8
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# R_pull = 1100 - (regval - 128)*2
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DCID_PULLDOWN_TRIM = 0x120b, Register8
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DCID_STATUS = 0x120c, R_DCID_STATUS
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# tip/ring sense
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TR_SENSE_CTRL1 = 0x1280, Register8
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TR_SENSE_CTRL2 = 0x1281, Register8
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RING_SENSE_CTRL = 0x1282, R_TR_SENSE_CTRL
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TIP_SENSE_CTRL = 0x1283, R_TR_SENSE_CTRL
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TR_SENSE_STATUS = 0x1288, R_TR_SENSE_STATUS
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HSBIAS_SC_AUTOCTL = 0x1470, R_HSBIAS_SC_AUTOCTL
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WAKE_CTRL = 0x1471, Register8 # guess (cs42l42)
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TIP_SENSE_CTRL2 = 0x1473, R_TIP_SENSE_CTRL2 # guess (cs42l42)
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MISC_DET_CTRL = 0x1474, R_MISC_DET_CTRL # guess (cs42l42)
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MIC_DET_CTRL2 = 0x1478, R_MIC_DET_CTRL2
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MIC_DET_CTRL4 = 0x1477, R_MIC_DET_CTRL4
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MIKEY_DET_STATUS = irange(0x147c, 2), Register8
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MIKEY_DET_IRQ_MASK = irange(0x1480, 2), Register8
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||||
MIKEY_DET_IRQ_STATUS = irange(0x1484, 2), Register8
|
||||
|
||||
MSM_BLOCK_EN3 = 0x1802, R_MSM_BLOCK_EN3
|
||||
HS_SWITCH_CTRL = 0x1812, R_HS_SWITCH_CTRL
|
||||
HS_CLAMP_DISABLE = 0x1813, R_HS_CLAMP_DISABLE
|
||||
ADC_CTRL = irange(0x2000, 4), Register8
|
||||
|
||||
DAC_CTRL1 = 0x3000, R_DAC_CTRL1
|
||||
DAC_CTRL2 = 0x3001, R_DAC_CTRL2
|
||||
DACA_VOL_LSB = 0x3004, Register8
|
||||
DACA_VOL_MSB = 0x3005, Register8 # sign bit
|
||||
DACB_VOL_LSB = 0x3006, Register8
|
||||
DACB_VOL_MSB = 0x3007, Register8 # sign bit
|
||||
HP_VOL_CTRL = 0x3020, Register8
|
||||
HP_CLAMP_CTRL = 0x3123, Register8
|
||||
|
||||
ASP_CTRL = 0x5000, Register8
|
||||
ASP_FSYNC_CTRL = irange(0x500f, 3), Register8
|
||||
ASP_DATA_CTRL = 0x5018, Register8
|
||||
|
||||
ASP_RX_EN = 0x5020, Register8
|
||||
ASP_TX_EN = 0x5024, Register8
|
||||
|
||||
ASP_RXSLOT_CH1_LSB = 0x5028, Register8
|
||||
ASP_RXSLOT_CH1_MSB = 0x5029, Register8
|
||||
|
||||
ASP_RXSLOT_CH2_LSB = 0x502c, Register8
|
||||
ASP_RXSLOT_CH2_MSB = 0x502d, Register8
|
||||
|
||||
ASP_TXSLOT_CH1_LSB = 0x5068, Register8
|
||||
ASP_TXSLOT_CH1_MSB = 0x5068, Register8
|
||||
|
|
@ -18,6 +18,10 @@ class SN012776(I2CRegMapDev):
|
|||
REGMAP = SN012776Regs
|
||||
ADDRESSING = (1, 1)
|
||||
|
||||
class CS42L84(I2CRegMapDev):
|
||||
REGMAP = CS42L84Regs
|
||||
ADDRESSING = (0, 2)
|
||||
|
||||
gpios = {}
|
||||
for node in u.adt["/arm-io"]:
|
||||
if node.name.endswith("gpio") or node.name.endswith("gpio0"):
|
||||
|
|
@ -37,7 +41,8 @@ for node in u.adt["/arm-io"]:
|
|||
|
||||
dcls = {
|
||||
"audio-control,tas5770": TAS5770,
|
||||
"audio-control,sn012776": SN012776
|
||||
"audio-control,sn012776": SN012776,
|
||||
"audio-control,cs42l84": CS42L84,
|
||||
}.get(devnode.compatible[0], None)
|
||||
|
||||
if not dcls:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue