2021-05-04 10:36:23 +00:00
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/* SPDX-License-Identifier: MIT */
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#include "hv.h"
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#include "assert.h"
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#include "cpu_regs.h"
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#include "exception.h"
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2021-09-15 14:22:42 +00:00
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#include "smp.h"
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2021-05-04 10:36:23 +00:00
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#include "string.h"
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2021-05-27 12:16:17 +00:00
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#include "uart.h"
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2021-05-04 10:36:23 +00:00
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#include "uartproxy.h"
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2021-09-21 04:17:00 +00:00
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#define TIME_ACCOUNTING
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2021-09-15 14:31:54 +00:00
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2021-09-15 14:16:28 +00:00
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extern spinlock_t bhl;
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2021-05-25 11:08:35 +00:00
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#define _SYSREG_ISS(_1, _2, op0, op1, CRn, CRm, op2) \
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(((op0) << ESR_ISS_MSR_OP0_SHIFT) | ((op1) << ESR_ISS_MSR_OP1_SHIFT) | \
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((CRn) << ESR_ISS_MSR_CRn_SHIFT) | ((CRm) << ESR_ISS_MSR_CRm_SHIFT) | \
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((op2) << ESR_ISS_MSR_OP2_SHIFT))
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#define SYSREG_ISS(...) _SYSREG_ISS(__VA_ARGS__)
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2021-09-15 14:26:14 +00:00
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#define D_PERCPU(t, x) t x[MAX_CPUS]
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#define PERCPU(x) x[mrs(TPIDR_EL2)]
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D_PERCPU(static bool, ipi_pending);
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D_PERCPU(static bool, pmc_pending);
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D_PERCPU(static u64, pmc_irq_mode);
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D_PERCPU(static u64, exc_entry_pmcr0_cnt);
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2021-05-25 11:08:35 +00:00
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2021-05-04 15:24:52 +00:00
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void hv_exit_guest(void) __attribute__((noreturn));
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2021-05-27 15:38:42 +00:00
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static u64 stolen_time = 0;
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static u64 exc_entry_time;
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2021-09-21 04:17:00 +00:00
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extern u32 hv_cpus_in_guest;
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2021-05-15 14:55:34 +00:00
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void hv_exc_proxy(u64 *regs, uartproxy_boot_reason_t reason, uartproxy_exc_code_t type, void *extra)
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2021-05-04 10:36:23 +00:00
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{
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2021-05-27 12:11:49 +00:00
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int from_el = FIELD_GET(SPSR_M, hv_get_spsr()) >> 2;
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2021-05-04 15:27:21 +00:00
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2021-05-27 12:16:17 +00:00
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hv_wdt_breadcrumb('P');
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2021-09-21 04:17:00 +00:00
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#ifdef TIME_ACCOUNTING
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/* Wait until all CPUs have entered the HV (max 1ms), to ensure they exit with an
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* updated timer offset. */
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hv_rendezvous();
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u64 entry_time = mrs(CNTPCT_EL0);
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#endif
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2021-05-04 10:36:23 +00:00
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struct uartproxy_exc_info exc_info = {
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2021-09-15 14:22:42 +00:00
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.cpu_id = smp_id(),
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2021-05-27 12:11:49 +00:00
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.spsr = hv_get_spsr(),
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.elr = hv_get_elr(),
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.esr = hv_get_esr(),
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.far = hv_get_far(),
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2021-05-29 18:29:52 +00:00
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.afsr1 = hv_get_afsr1(),
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2021-05-04 10:36:23 +00:00
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.sp = {mrs(SP_EL0), mrs(SP_EL1), 0},
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.mpidr = mrs(MPIDR_EL1),
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2021-05-27 12:11:49 +00:00
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.elr_phys = hv_translate(hv_get_elr(), false, false),
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.far_phys = hv_translate(hv_get_far(), false, false),
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2021-05-04 18:27:19 +00:00
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.sp_phys = hv_translate(from_el == 0 ? mrs(SP_EL0) : mrs(SP_EL1), false, false),
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2021-05-15 14:55:34 +00:00
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.extra = extra,
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2021-05-04 10:36:23 +00:00
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};
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memcpy(exc_info.regs, regs, sizeof(exc_info.regs));
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struct uartproxy_msg_start start = {
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2021-05-15 14:55:34 +00:00
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.reason = reason,
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2021-05-04 10:36:23 +00:00
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.code = type,
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.info = &exc_info,
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};
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2021-05-27 12:16:17 +00:00
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hv_wdt_suspend();
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2021-05-04 10:36:23 +00:00
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int ret = uartproxy_run(&start);
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2021-05-27 12:16:17 +00:00
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hv_wdt_resume();
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2021-05-04 10:36:23 +00:00
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2021-05-04 15:24:52 +00:00
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switch (ret) {
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case EXC_RET_HANDLED:
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memcpy(regs, exc_info.regs, sizeof(exc_info.regs));
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2021-05-27 12:11:49 +00:00
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hv_set_spsr(exc_info.spsr);
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hv_set_elr(exc_info.elr);
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2021-05-04 15:24:52 +00:00
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msr(SP_EL0, exc_info.sp[0]);
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msr(SP_EL1, exc_info.sp[1]);
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2021-05-27 12:16:17 +00:00
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hv_wdt_breadcrumb('p');
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2021-09-21 04:17:00 +00:00
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#ifdef TIME_ACCOUNTING
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u64 lost = mrs(CNTPCT_EL0) - entry_time;
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stolen_time += lost;
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#endif
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2021-05-04 15:24:52 +00:00
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return;
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case EXC_EXIT_GUEST:
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2021-09-15 14:16:28 +00:00
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spin_unlock(&bhl);
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2021-05-04 15:24:52 +00:00
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hv_exit_guest();
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default:
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printf("Guest exception not handled, rebooting.\n");
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print_regs(regs, 0);
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2021-05-04 18:21:48 +00:00
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flush_and_reboot();
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2021-05-04 10:36:23 +00:00
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}
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}
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2021-05-25 11:08:35 +00:00
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static void hv_update_fiq(void)
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{
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u64 hcr = mrs(HCR_EL2);
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bool fiq_pending = false;
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if (mrs(CNTP_CTL_EL02) == (CNTx_CTL_ISTATUS | CNTx_CTL_ENABLE)) {
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fiq_pending = true;
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2021-05-27 15:38:11 +00:00
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reg_clr(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENA_ENA_P);
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2021-05-25 11:08:35 +00:00
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} else {
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2021-05-27 15:38:11 +00:00
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reg_set(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENA_ENA_P);
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2021-05-25 11:08:35 +00:00
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}
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if (mrs(CNTV_CTL_EL02) == (CNTx_CTL_ISTATUS | CNTx_CTL_ENABLE)) {
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fiq_pending = true;
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2021-05-27 15:38:11 +00:00
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reg_clr(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENA_ENA_V);
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2021-05-25 11:08:35 +00:00
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} else {
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2021-05-27 15:38:11 +00:00
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reg_set(SYS_IMP_APL_VM_TMR_FIQ_ENA_EL2, VM_TMR_FIQ_ENA_ENA_V);
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2021-05-25 11:08:35 +00:00
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}
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2021-09-15 14:26:14 +00:00
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fiq_pending |= PERCPU(ipi_pending) || PERCPU(pmc_pending);
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2021-05-25 11:08:35 +00:00
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sysop("isb");
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if ((hcr & HCR_VF) && !fiq_pending) {
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hv_write_hcr(hcr & ~HCR_VF);
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} else if (!(hcr & HCR_VF) && fiq_pending) {
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hv_write_hcr(hcr | HCR_VF);
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}
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}
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2021-05-27 15:37:48 +00:00
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#define SYSREG_MAP(sr, to) \
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case SYSREG_ISS(sr): \
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if (is_read) \
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regs[rt] = _mrs(sr_tkn(to)); \
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else \
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_msr(sr_tkn(to), regs[rt]); \
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return true;
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2021-05-25 11:08:35 +00:00
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#define SYSREG_PASS(sr) \
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case SYSREG_ISS(sr): \
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if (is_read) \
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regs[rt] = _mrs(sr_tkn(sr)); \
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else \
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_msr(sr_tkn(sr), regs[rt]); \
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return true;
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static bool hv_handle_msr(u64 *regs, u64 iss)
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{
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u64 reg = iss & (ESR_ISS_MSR_OP0 | ESR_ISS_MSR_OP2 | ESR_ISS_MSR_OP1 | ESR_ISS_MSR_CRn |
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ESR_ISS_MSR_CRm);
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u64 rt = FIELD_GET(ESR_ISS_MSR_Rt, iss);
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bool is_read = iss & ESR_ISS_MSR_DIR;
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regs[31] = 0;
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switch (reg) {
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2021-05-27 17:36:06 +00:00
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/* Some kind of timer */
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SYSREG_PASS(sys_reg(3, 7, 15, 1, 1));
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2021-05-27 15:37:48 +00:00
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/* Noisy traps */
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SYSREG_MAP(SYS_ACTLR_EL1, SYS_IMP_APL_ACTLR_EL12)
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2021-05-29 18:37:12 +00:00
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SYSREG_PASS(SYS_IMP_APL_HID4)
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SYSREG_PASS(SYS_IMP_APL_EHID4)
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2021-06-03 11:50:53 +00:00
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/* pass through PMU handling */
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SYSREG_PASS(SYS_IMP_APL_PMCR1)
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SYSREG_PASS(SYS_IMP_APL_PMCR2)
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SYSREG_PASS(SYS_IMP_APL_PMCR3)
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SYSREG_PASS(SYS_IMP_APL_PMCR4)
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SYSREG_PASS(SYS_IMP_APL_PMESR0)
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SYSREG_PASS(SYS_IMP_APL_PMESR1)
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SYSREG_PASS(SYS_IMP_APL_PMSR)
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#ifndef DEBUG_PMU_IRQ
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SYSREG_PASS(SYS_IMP_APL_PMC0)
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#endif
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SYSREG_PASS(SYS_IMP_APL_PMC1)
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SYSREG_PASS(SYS_IMP_APL_PMC2)
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SYSREG_PASS(SYS_IMP_APL_PMC3)
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SYSREG_PASS(SYS_IMP_APL_PMC4)
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SYSREG_PASS(SYS_IMP_APL_PMC5)
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SYSREG_PASS(SYS_IMP_APL_PMC6)
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SYSREG_PASS(SYS_IMP_APL_PMC7)
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SYSREG_PASS(SYS_IMP_APL_PMC8)
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SYSREG_PASS(SYS_IMP_APL_PMC9)
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2021-09-18 13:27:27 +00:00
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/* Handle this one here because m1n1/Linux (will) use it for explicit cpuidle.
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* We can pass it through; going into deep sleep doesn't break the HV since we
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* don't do any wfis that assume otherwise in m1n1. */
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SYSREG_PASS(SYS_IMP_APL_CYC_OVRD)
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2021-05-25 11:08:35 +00:00
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/* IPI handling */
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2021-05-27 15:38:11 +00:00
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SYSREG_PASS(SYS_IMP_APL_IPI_RR_LOCAL_EL1)
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SYSREG_PASS(SYS_IMP_APL_IPI_RR_GLOBAL_EL1)
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SYSREG_PASS(SYS_IMP_APL_IPI_CR_EL1)
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case SYSREG_ISS(SYS_IMP_APL_IPI_SR_EL1):
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2021-05-25 11:08:35 +00:00
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if (is_read)
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2021-09-15 14:26:14 +00:00
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regs[rt] = PERCPU(ipi_pending) ? IPI_SR_PENDING : 0;
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2021-05-25 11:08:35 +00:00
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else if (regs[rt] & IPI_SR_PENDING)
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2021-09-15 14:26:14 +00:00
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PERCPU(ipi_pending) = false;
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2021-05-25 11:08:35 +00:00
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return true;
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2021-06-03 11:50:53 +00:00
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/* shadow the interrupt mode and state flag */
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case SYSREG_ISS(SYS_IMP_APL_PMCR0):
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if (is_read) {
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2021-09-15 14:26:14 +00:00
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u64 val = (mrs(SYS_IMP_APL_PMCR0) & ~PMCR0_IMODE_MASK) | PERCPU(pmc_irq_mode);
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regs[rt] =
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val | (PERCPU(pmc_pending) ? PMCR0_IACT : 0) | PERCPU(exc_entry_pmcr0_cnt);
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2021-06-03 11:50:53 +00:00
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} else {
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2021-09-15 14:26:14 +00:00
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PERCPU(pmc_pending) = !!(regs[rt] & PMCR0_IACT);
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PERCPU(pmc_irq_mode) = regs[rt] & PMCR0_IMODE_MASK;
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PERCPU(exc_entry_pmcr0_cnt) = regs[rt] & PMCR0_CNT_MASK;
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msr(SYS_IMP_APL_PMCR0, regs[rt] & ~PERCPU(exc_entry_pmcr0_cnt));
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2021-06-03 11:50:53 +00:00
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}
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return true;
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#ifdef DEBUG_PMU_IRQ
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case SYSREG_ISS(SYS_IMP_APL_PMC0):
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if (is_read) {
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regs[rt] = mrs(SYS_IMP_APL_PMC0);
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} else {
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msr(SYS_IMP_APL_PMC0, regs[rt]);
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printf("msr(SYS_IMP_APL_PMC0, 0x%04lx_%08lx)\n", regs[rt] >> 32,
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regs[rt] & 0xFFFFFFFF);
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}
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return true;
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#endif
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2021-08-14 07:27:16 +00:00
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/* M1RACLES reg, handle here due to silly 12.0 "mitigation" */
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case SYSREG_ISS(sys_reg(3, 5, 15, 10, 1)):
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if (is_read)
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regs[rt] = 0;
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return true;
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2021-05-25 11:08:35 +00:00
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}
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return false;
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}
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2021-05-27 15:38:42 +00:00
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static void hv_exc_entry(u64 *regs)
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{
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UNUSED(regs);
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2021-09-21 04:17:00 +00:00
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__atomic_sub_fetch(&hv_cpus_in_guest, 1, __ATOMIC_ACQUIRE);
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2021-09-15 14:16:28 +00:00
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spin_lock(&bhl);
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2021-05-27 15:38:42 +00:00
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hv_wdt_breadcrumb('X');
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exc_entry_time = mrs(CNTPCT_EL0);
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2021-06-05 10:37:37 +00:00
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/* disable PMU counters in the hypervisor */
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u64 pmcr0 = mrs(SYS_IMP_APL_PMCR0);
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2021-09-15 14:26:14 +00:00
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PERCPU(exc_entry_pmcr0_cnt) = pmcr0 & PMCR0_CNT_MASK;
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2021-06-05 10:37:37 +00:00
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msr(SYS_IMP_APL_PMCR0, pmcr0 & ~PMCR0_CNT_MASK);
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2021-05-27 15:38:42 +00:00
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}
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2021-05-25 11:07:02 +00:00
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static void hv_exc_exit(u64 *regs)
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{
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2021-05-27 16:24:29 +00:00
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UNUSED(regs);
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2021-05-27 12:16:17 +00:00
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hv_wdt_breadcrumb('x');
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2021-05-25 11:08:35 +00:00
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hv_update_fiq();
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2021-09-15 14:26:14 +00:00
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/* reenable PMU counters */
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reg_set(SYS_IMP_APL_PMCR0, PERCPU(exc_entry_pmcr0_cnt));
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2021-05-27 15:38:42 +00:00
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msr(CNTVOFF_EL2, stolen_time);
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2021-09-15 14:16:28 +00:00
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spin_unlock(&bhl);
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2021-09-21 04:17:00 +00:00
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__atomic_add_fetch(&hv_cpus_in_guest, 1, __ATOMIC_ACQUIRE);
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2021-05-25 11:07:02 +00:00
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}
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2021-05-04 10:36:23 +00:00
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void hv_exc_sync(u64 *regs)
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{
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2021-05-27 12:16:17 +00:00
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hv_wdt_breadcrumb('S');
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2021-05-27 15:38:42 +00:00
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hv_exc_entry(regs);
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2021-05-25 10:57:46 +00:00
|
|
|
bool handled = false;
|
2021-05-27 12:11:49 +00:00
|
|
|
u64 esr = hv_get_esr();
|
2021-05-04 10:36:23 +00:00
|
|
|
u32 ec = FIELD_GET(ESR_EC, esr);
|
|
|
|
|
|
|
|
switch (ec) {
|
|
|
|
case ESR_EC_DABORT_LOWER:
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('D');
|
2021-05-25 10:57:46 +00:00
|
|
|
handled = hv_handle_dabort(regs);
|
2021-05-04 10:36:23 +00:00
|
|
|
break;
|
2021-05-25 11:08:35 +00:00
|
|
|
case ESR_EC_MSR:
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('M');
|
2021-05-25 11:08:35 +00:00
|
|
|
handled = hv_handle_msr(regs, FIELD_GET(ESR_ISS, esr));
|
|
|
|
break;
|
|
|
|
case ESR_EC_IMPDEF:
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('A');
|
2021-05-25 11:08:35 +00:00
|
|
|
switch (FIELD_GET(ESR_ISS, esr)) {
|
|
|
|
case ESR_ISS_IMPDEF_MSR:
|
2021-05-29 18:29:52 +00:00
|
|
|
handled = hv_handle_msr(regs, hv_get_afsr1());
|
2021-05-25 11:08:35 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2021-05-04 10:36:23 +00:00
|
|
|
}
|
|
|
|
|
2021-05-27 12:16:17 +00:00
|
|
|
if (handled) {
|
|
|
|
hv_wdt_breadcrumb('+');
|
2021-05-27 12:11:49 +00:00
|
|
|
hv_set_elr(hv_get_elr() + 4);
|
2021-05-27 12:16:17 +00:00
|
|
|
} else {
|
|
|
|
hv_wdt_breadcrumb('-');
|
2021-05-25 10:57:46 +00:00
|
|
|
hv_exc_proxy(regs, START_EXCEPTION_LOWER, EXC_SYNC, NULL);
|
2021-05-27 12:16:17 +00:00
|
|
|
}
|
2021-05-25 11:07:02 +00:00
|
|
|
|
|
|
|
hv_exc_exit(regs);
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('s');
|
2021-05-04 10:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void hv_exc_irq(u64 *regs)
|
|
|
|
{
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('I');
|
2021-05-27 15:38:42 +00:00
|
|
|
hv_exc_entry(regs);
|
2021-05-15 14:55:34 +00:00
|
|
|
hv_exc_proxy(regs, START_EXCEPTION_LOWER, EXC_IRQ, NULL);
|
2021-05-25 11:07:02 +00:00
|
|
|
hv_exc_exit(regs);
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('i');
|
2021-05-04 10:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void hv_exc_fiq(u64 *regs)
|
|
|
|
{
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('F');
|
2021-05-27 15:38:42 +00:00
|
|
|
hv_exc_entry(regs);
|
2021-05-25 11:04:20 +00:00
|
|
|
if (mrs(CNTP_CTL_EL0) == (CNTx_CTL_ISTATUS | CNTx_CTL_ENABLE)) {
|
|
|
|
msr(CNTP_CTL_EL0, CNTx_CTL_ISTATUS | CNTx_CTL_IMASK | CNTx_CTL_ENABLE);
|
2021-05-27 16:24:29 +00:00
|
|
|
hv_tick(regs);
|
2021-05-25 11:04:20 +00:00
|
|
|
hv_arm_tick();
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mrs(CNTV_CTL_EL0) == (CNTx_CTL_ISTATUS | CNTx_CTL_ENABLE)) {
|
|
|
|
msr(CNTV_CTL_EL0, CNTx_CTL_ISTATUS | CNTx_CTL_IMASK | CNTx_CTL_ENABLE);
|
|
|
|
hv_exc_proxy(regs, START_HV, HV_VTIMER, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
u64 reg = mrs(SYS_IMP_APL_PMCR0);
|
|
|
|
if ((reg & (PMCR0_IMODE_MASK | PMCR0_IACT)) == (PMCR0_IMODE_FIQ | PMCR0_IACT)) {
|
2021-06-03 11:50:53 +00:00
|
|
|
#ifdef DEBUG_PMU_IRQ
|
|
|
|
printf("[FIQ] PMC IRQ, masking and delivering to the guest\n");
|
|
|
|
#endif
|
2021-05-25 11:04:20 +00:00
|
|
|
reg_clr(SYS_IMP_APL_PMCR0, PMCR0_IACT | PMCR0_IMODE_MASK);
|
2021-09-15 14:26:14 +00:00
|
|
|
PERCPU(pmc_pending) = true;
|
2021-05-25 11:04:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
reg = mrs(SYS_IMP_APL_UPMCR0);
|
|
|
|
if ((reg & UPMCR0_IMODE_MASK) == UPMCR0_IMODE_FIQ && (mrs(SYS_IMP_APL_UPMSR) & UPMSR_IACT)) {
|
|
|
|
printf("[FIQ] UPMC IRQ, masking");
|
|
|
|
reg_clr(SYS_IMP_APL_UPMCR0, UPMCR0_IMODE_MASK);
|
|
|
|
hv_exc_proxy(regs, START_EXCEPTION_LOWER, EXC_FIQ, NULL);
|
|
|
|
}
|
2021-05-25 11:08:35 +00:00
|
|
|
|
2021-05-27 15:38:11 +00:00
|
|
|
if (mrs(SYS_IMP_APL_IPI_SR_EL1) & IPI_SR_PENDING) {
|
2021-09-15 14:26:14 +00:00
|
|
|
PERCPU(ipi_pending) = true;
|
2021-05-27 15:38:11 +00:00
|
|
|
msr(SYS_IMP_APL_IPI_SR_EL1, IPI_SR_PENDING);
|
2021-05-25 11:08:35 +00:00
|
|
|
sysop("isb");
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handles guest timers
|
2021-05-25 11:07:02 +00:00
|
|
|
hv_exc_exit(regs);
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('f');
|
2021-05-04 10:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void hv_exc_serr(u64 *regs)
|
|
|
|
{
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('E');
|
2021-05-27 15:38:42 +00:00
|
|
|
hv_exc_entry(regs);
|
2021-05-15 14:55:34 +00:00
|
|
|
hv_exc_proxy(regs, START_EXCEPTION_LOWER, EXC_SERROR, NULL);
|
2021-05-25 11:07:02 +00:00
|
|
|
hv_exc_exit(regs);
|
2021-05-27 12:16:17 +00:00
|
|
|
hv_wdt_breadcrumb('e');
|
2021-05-04 10:36:23 +00:00
|
|
|
}
|