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ff36fd8591
add support for the AMD db1550 board * Patch by Travis Sawyer, 15 Sep 2004: Add CONFIG_SERIAL_MULTI support for ppc4xx, update README.serial_multi
1054 lines
29 KiB
C
1054 lines
29 KiB
C
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*------------------------------------------------------------------------------+ */
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/*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*/
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/*------------------------------------------------------------------------------- */
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/*
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* Travis Sawyer 15 September 2004
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* Added CONFIG_SERIAL_MULTI support
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*/
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#include <common.h>
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#include <commproc.h>
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#include <asm/processor.h>
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#include <watchdog.h>
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#include "vecnum.h"
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#ifdef CONFIG_SERIAL_MULTI
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#include <serial.h>
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#endif
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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#include <malloc.h>
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#endif
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/*****************************************************************************/
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#ifdef CONFIG_IOP480
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#define SPU_BASE 0x40000000
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#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
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#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
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#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
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#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
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#define spu_BRateDivh 0x10 /* Baud rate divisor high */
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#define spu_BRateDivl 0x14 /* Baud rate divisor low */
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#define spu_CtlReg 0x18 /* Control Register */
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#define spu_RxCmd 0x1c /* Rx Command Register */
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#define spu_TxCmd 0x20 /* Tx Command Register */
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#define spu_RxBuff 0x24 /* Rx data buffer */
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#define spu_TxBuff 0x24 /* Tx data buffer */
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/*-----------------------------------------------------------------------------+
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| Line Status Register.
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+-----------------------------------------------------------------------------*/
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#define asyncLSRport1 0x40000000
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#define asyncLSRport1set 0x40000004
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#define asyncLSRDataReady 0x80
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#define asyncLSRFramingError 0x40
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#define asyncLSROverrunError 0x20
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#define asyncLSRParityError 0x10
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#define asyncLSRBreakInterrupt 0x08
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#define asyncLSRTxHoldEmpty 0x04
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#define asyncLSRTxShiftEmpty 0x02
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/*-----------------------------------------------------------------------------+
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| Handshake Status Register.
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+-----------------------------------------------------------------------------*/
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#define asyncHSRport1 0x40000008
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#define asyncHSRport1set 0x4000000c
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#define asyncHSRDsr 0x80
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#define asyncLSRCts 0x40
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/*-----------------------------------------------------------------------------+
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| Control Register.
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+-----------------------------------------------------------------------------*/
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#define asyncCRport1 0x40000018
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#define asyncCRNormal 0x00
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#define asyncCRLoopback 0x40
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#define asyncCRAutoEcho 0x80
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#define asyncCRDtr 0x20
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#define asyncCRRts 0x10
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#define asyncCRWordLength7 0x00
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#define asyncCRWordLength8 0x08
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#define asyncCRParityDisable 0x00
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#define asyncCRParityEnable 0x04
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#define asyncCREvenParity 0x00
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#define asyncCROddParity 0x02
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#define asyncCRStopBitsOne 0x00
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#define asyncCRStopBitsTwo 0x01
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#define asyncCRDisableDtrRts 0x00
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/*-----------------------------------------------------------------------------+
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| Receiver Command Register.
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+-----------------------------------------------------------------------------*/
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#define asyncRCRport1 0x4000001c
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#define asyncRCRDisable 0x00
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#define asyncRCREnable 0x80
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#define asyncRCRIntDisable 0x00
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#define asyncRCRIntEnabled 0x20
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#define asyncRCRDMACh2 0x40
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#define asyncRCRDMACh3 0x60
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#define asyncRCRErrorInt 0x10
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#define asyncRCRPauseEnable 0x08
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/*-----------------------------------------------------------------------------+
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| Transmitter Command Register.
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+-----------------------------------------------------------------------------*/
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#define asyncTCRport1 0x40000020
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#define asyncTCRDisable 0x00
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#define asyncTCREnable 0x80
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#define asyncTCRIntDisable 0x00
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#define asyncTCRIntEnabled 0x20
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#define asyncTCRDMACh2 0x40
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#define asyncTCRDMACh3 0x60
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#define asyncTCRTxEmpty 0x10
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#define asyncTCRErrorInt 0x08
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#define asyncTCRStopPause 0x04
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#define asyncTCRBreakGen 0x02
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/*-----------------------------------------------------------------------------+
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| Miscellanies defines.
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+-----------------------------------------------------------------------------*/
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#define asyncTxBufferport1 0x40000024
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#define asyncRxBufferport1 0x40000024
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#define asyncDLABLsbport1 0x40000014
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#define asyncDLABMsbport1 0x40000010
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#define asyncXOFFchar 0x13
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#define asyncXONchar 0x11
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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int serial_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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volatile char val;
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unsigned short br_reg;
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br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
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/*
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* Init onboard UART
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*/
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out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
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out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
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out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
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out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
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out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
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out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
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out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
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val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
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return (0);
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}
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void serial_setbrg (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned short br_reg;
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br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
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out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
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out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
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}
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void serial_putc (const char c)
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{
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if (c == '\n')
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serial_putc ('\r');
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/* load status from handshake register */
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if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
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out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
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out8 (SPU_BASE + spu_TxBuff, c); /* Put char */
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while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) {
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if (in8 (SPU_BASE + spu_Handshk_rc) != 00)
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out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
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}
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}
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void serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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int serial_getc ()
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{
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unsigned char status = 0;
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while (1) {
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status = in8 (asyncLSRport1);
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if ((status & asyncLSRDataReady) != 0x0) {
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break;
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}
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if ((status & ( asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt )) != 0) {
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(void) out8 (asyncLSRport1,
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asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt );
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}
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}
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return (0x000000ff & (int) in8 (asyncRxBufferport1));
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}
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int serial_tstc ()
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{
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unsigned char status;
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status = in8 (asyncLSRport1);
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if ((status & asyncLSRDataReady) != 0x0) {
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return (1);
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}
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if ((status & ( asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt )) != 0) {
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(void) out8 (asyncLSRport1,
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asyncLSRFramingError |
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asyncLSROverrunError |
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asyncLSRParityError |
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asyncLSRBreakInterrupt);
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}
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return 0;
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}
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#endif /* CONFIG_IOP480 */
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/*****************************************************************************/
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
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#if defined(CONFIG_440)
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#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
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#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300
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#if defined(CONFIG_440_GX)
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#define CR0_MASK 0xdfffffff
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#define CR0_EXTCLK_ENA 0x00800000
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#define CR0_UDIV_POS 0
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#else
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#define CR0_MASK 0x3fff0000
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#define CR0_EXTCLK_ENA 0x00600000
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#define CR0_UDIV_POS 16
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#endif /* CONFIG_440_GX */
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#elif defined(CONFIG_405EP)
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define UCR0_MASK 0x0000007f
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#define UCR1_MASK 0x00007f00
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#define UCR0_UDIV_POS 0
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#define UCR1_UDIV_POS 8
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#define UDIV_MAX 127
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#else /* CONFIG_405GP || CONFIG_405CR */
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#define UART0_BASE 0xef600300
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#define UART1_BASE 0xef600400
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#define CR0_MASK 0x00001fff
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#define CR0_EXTCLK_ENA 0x000000c0
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#define CR0_UDIV_POS 1
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#define UDIV_MAX 32
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#endif
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/* using serial port 0 or 1 as U-Boot console ? */
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#if defined(CONFIG_UART1_CONSOLE)
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#define ACTING_UART0_BASE UART1_BASE
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#define ACTING_UART1_BASE UART0_BASE
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#if defined(CONFIG_440_GX)
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#define UART0_SDR sdr_uart1
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#define UART1_SDR sdr_uart0
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#endif /* CONFIG_440_GX */
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#else
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#define ACTING_UART0_BASE UART0_BASE
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#define ACTING_UART1_BASE UART1_BASE
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#if defined(CONFIG_440_GX)
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#define UART0_SDR sdr_uart0
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#define UART1_SDR sdr_uart1
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#endif /* CONFIG_440_GX */
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#endif
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#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
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#error "External serial clock not supported on IBM PPC405EP!"
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#endif
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#define UART_RBR 0x00
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#define UART_THR 0x00
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/*-----------------------------------------------------------------------------+
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| Line Status Register.
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+-----------------------------------------------------------------------------*/
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/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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#define asyncLSRFramingError1 0x08
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#define asyncLSRBreakInterrupt1 0x10
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#define asyncLSRTxHoldEmpty1 0x20
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#define asyncLSRTxShiftEmpty1 0x40
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#define asyncLSRRxFifoError1 0x80
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/*-----------------------------------------------------------------------------+
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| Miscellanies defines.
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+-----------------------------------------------------------------------------*/
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/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
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/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
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#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
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/*-----------------------------------------------------------------------------+
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| Fifo
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+-----------------------------------------------------------------------------*/
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typedef struct {
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char *rx_buffer;
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ulong rx_put;
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ulong rx_get;
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} serial_buffer_t;
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volatile static serial_buffer_t buf_info;
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#endif
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#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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unsigned short *pbdiv )
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{
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sys_info_t sysinfo;
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unsigned long div; /* total divisor udiv * bdiv */
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unsigned long umin; /* minimum udiv */
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unsigned short diff; /* smallest diff */
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unsigned long udiv; /* best udiv */
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unsigned short idiff; /* current diff */
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unsigned short ibdiv; /* current bdiv */
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unsigned long i;
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unsigned long est; /* current estimate */
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get_sys_info( &sysinfo );
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udiv = 32; /* Assume lowest possible serial clk */
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div = sysinfo.freqPLB/(16*baudrate); /* total divisor */
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umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */
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diff = 32; /* highest possible */
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/* i is the test udiv value -- start with the largest
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* possible (32) to minimize serial clock and constrain
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* search to umin.
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*/
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for( i = 32; i > umin; i-- ){
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ibdiv = div/i;
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est = i * ibdiv;
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idiff = (est > div) ? (est-div) : (div-est);
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if( idiff == 0 ){
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udiv = i;
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break; /* can't do better */
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}
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else if( idiff < diff ){
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udiv = i; /* best so far */
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diff = idiff; /* update lowest diff*/
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}
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}
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*pudiv = udiv;
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*pbdiv = div/udiv;
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}
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#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
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|
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/*
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* Minimal serial functions needed to use one of the SMC ports
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* as serial console interface.
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*/
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#if defined(CONFIG_440)
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#if defined(CONFIG_SERIAL_MULTI)
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int serial_init_dev (unsigned long dev_base)
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#else
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int serial_init(void)
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#endif
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long reg;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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#ifdef CFG_EXT_SERIAL_CLOCK
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unsigned long tmp;
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#endif
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#if defined(CONFIG_440_GX)
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#if defined(CONFIG_SERIAL_MULTI)
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if (UART0_BASE == dev_base) {
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mfsdr(UART0_SDR,reg);
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reg &= ~CR0_MASK;
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} else {
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mfsdr(UART1_SDR,reg);
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reg &= ~CR0_MASK;
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}
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#else
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mfsdr(UART0_SDR,reg);
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reg &= ~CR0_MASK;
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#endif
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#else
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reg = mfdcr(cntrl0) & ~CR0_MASK;
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#endif /* CONFIG_440_GX */
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#ifdef CFG_EXT_SERIAL_CLOCK
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reg |= CR0_EXTCLK_ENA;
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udiv = 1;
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tmp = gd->baudrate * 16;
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bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
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#else
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/* For 440, the cpu clock is on divider chain A, UART on divider
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* chain B ... so cpu clock is irrelevant. Get the "optimized"
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* values that are subject to the 1/2 opb clock constraint
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*/
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serial_divs (gd->baudrate, &udiv, &bdiv);
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#endif
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#if defined(CONFIG_440_GX)
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reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
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#if defined(CONFIG_SERIAL_MULTI)
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if (UART0_BASE == dev_base) {
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mtsdr (UART0_SDR,reg);
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} else {
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mtsdr (UART1_SDR,reg);
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}
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#else
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mtsdr (UART0_SDR,reg);
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#endif
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#else
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reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
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mtdcr (cntrl0, reg);
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#endif
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#if defined(CONFIG_SERIAL_MULTI)
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out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
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out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
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out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
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out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
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out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
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out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
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val = in8 (dev_base + UART_LSR); /* clear line status */
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val = in8 (dev_base + UART_RBR); /* read receive buffer */
|
|
out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
|
|
out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
|
|
#else
|
|
out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
|
out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
|
|
out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
|
out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
|
out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
|
|
out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
|
|
val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
|
|
out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
|
|
out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
|
#endif
|
|
return (0);
|
|
}
|
|
|
|
#else /* !defined(CONFIG_440) */
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
int serial_init_dev (unsigned long dev_base)
|
|
#else
|
|
int serial_init (void)
|
|
#endif
|
|
{
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
unsigned long reg;
|
|
unsigned long tmp;
|
|
unsigned long clk;
|
|
unsigned long udiv;
|
|
unsigned short bdiv;
|
|
volatile char val;
|
|
|
|
#ifdef CONFIG_405EP
|
|
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
|
|
clk = gd->cpu_clk;
|
|
tmp = CFG_BASE_BAUD * 16;
|
|
udiv = (clk + tmp / 2) / tmp;
|
|
if (udiv > UDIV_MAX) /* max. n bits for udiv */
|
|
udiv = UDIV_MAX;
|
|
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
|
|
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
|
|
mtdcr (cpc0_ucr, reg);
|
|
#else /* CONFIG_405EP */
|
|
reg = mfdcr(cntrl0) & ~CR0_MASK;
|
|
#ifdef CFG_EXT_SERIAL_CLOCK
|
|
clk = CFG_EXT_SERIAL_CLOCK;
|
|
udiv = 1;
|
|
reg |= CR0_EXTCLK_ENA;
|
|
#else
|
|
clk = gd->cpu_clk;
|
|
#ifdef CFG_405_UART_ERRATA_59
|
|
udiv = 31; /* Errata 59: stuck at 31 */
|
|
#else
|
|
tmp = CFG_BASE_BAUD * 16;
|
|
udiv = (clk + tmp / 2) / tmp;
|
|
if (udiv > UDIV_MAX) /* max. n bits for udiv */
|
|
udiv = UDIV_MAX;
|
|
#endif
|
|
#endif
|
|
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
|
|
mtdcr (cntrl0, reg);
|
|
#endif /* CONFIG_405EP */
|
|
|
|
tmp = gd->baudrate * udiv * 16;
|
|
bdiv = (clk + tmp / 2) / tmp;
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
|
out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
|
out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
|
out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
|
out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
|
|
out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
val = in8 (dev_base + UART_LSR); /* clear line status */
|
|
val = in8 (dev_base + UART_RBR); /* read receive buffer */
|
|
out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
|
|
out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
|
|
#else
|
|
out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
|
out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
|
|
out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
|
out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
|
out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
|
|
out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
|
|
val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
|
|
out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
|
|
out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
|
#endif
|
|
return (0);
|
|
}
|
|
|
|
#endif /* if defined(CONFIG_440) */
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
void serial_setbrg_dev (unsigned long dev_base)
|
|
#else
|
|
void serial_setbrg (void)
|
|
#endif
|
|
{
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
unsigned long tmp;
|
|
unsigned long clk;
|
|
unsigned long udiv;
|
|
unsigned short bdiv;
|
|
|
|
#ifdef CFG_EXT_SERIAL_CLOCK
|
|
clk = CFG_EXT_SERIAL_CLOCK;
|
|
#else
|
|
clk = gd->cpu_clk;
|
|
#endif
|
|
|
|
#ifdef CONFIG_405EP
|
|
udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
|
|
#else
|
|
udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
|
|
#endif /* CONFIG_405EP */
|
|
tmp = gd->baudrate * udiv * 16;
|
|
bdiv = (clk + tmp / 2) / tmp;
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
|
out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
|
out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
|
out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
|
#else
|
|
out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
|
out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
|
|
out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
|
out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
|
#endif
|
|
}
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
void serial_putc_dev (unsigned long dev_base, const char c)
|
|
#else
|
|
void serial_putc (const char c)
|
|
#endif
|
|
{
|
|
int i;
|
|
|
|
if (c == '\n')
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
serial_putc_dev (dev_base, '\r');
|
|
#else
|
|
serial_putc ('\r');
|
|
#endif
|
|
|
|
/* check THRE bit, wait for transmiter available */
|
|
for (i = 1; i < 3500; i++) {
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
|
|
#else
|
|
if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
|
|
#endif
|
|
break;
|
|
udelay (100);
|
|
}
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
out8 (dev_base + UART_THR, c); /* put character out */
|
|
#else
|
|
out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
|
|
#endif
|
|
}
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
void serial_puts_dev (unsigned long dev_base, const char *s)
|
|
#else
|
|
void serial_puts (const char *s)
|
|
#endif
|
|
{
|
|
while (*s) {
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
serial_putc_dev (dev_base, *s++);
|
|
#else
|
|
serial_putc (*s++);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
int serial_getc_dev (unsigned long dev_base)
|
|
#else
|
|
int serial_getc (void)
|
|
#endif
|
|
{
|
|
unsigned char status = 0;
|
|
|
|
while (1) {
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
|
#endif /* CONFIG_HW_WATCHDOG */
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
status = in8 (dev_base + UART_LSR);
|
|
#else
|
|
status = in8 (ACTING_UART0_BASE + UART_LSR);
|
|
#endif
|
|
if ((status & asyncLSRDataReady1) != 0x0) {
|
|
break;
|
|
}
|
|
if ((status & ( asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1 )) != 0) {
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
out8 (dev_base + UART_LSR,
|
|
#else
|
|
out8 (ACTING_UART0_BASE + UART_LSR,
|
|
#endif
|
|
asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1);
|
|
}
|
|
}
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
return (0x000000ff & (int) in8 (dev_base));
|
|
#else
|
|
return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
|
|
#endif
|
|
}
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
int serial_tstc_dev (unsigned long dev_base)
|
|
#else
|
|
int serial_tstc (void)
|
|
#endif
|
|
{
|
|
unsigned char status;
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
status = in8 (dev_base + UART_LSR);
|
|
#else
|
|
status = in8 (ACTING_UART0_BASE + UART_LSR);
|
|
#endif
|
|
if ((status & asyncLSRDataReady1) != 0x0) {
|
|
return (1);
|
|
}
|
|
if ((status & ( asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1 )) != 0) {
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
out8 (dev_base + UART_LSR,
|
|
#else
|
|
out8 (ACTING_UART0_BASE + UART_LSR,
|
|
#endif
|
|
asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
|
|
|
void serial_isr (void *arg)
|
|
{
|
|
int space;
|
|
int c;
|
|
const int rx_get = buf_info.rx_get;
|
|
int rx_put = buf_info.rx_put;
|
|
|
|
if (rx_get <= rx_put) {
|
|
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
|
} else {
|
|
space = rx_get - rx_put;
|
|
}
|
|
while (serial_tstc_dev (ACTING_UART0_BASE)) {
|
|
c = serial_getc_dev (ACTING_UART0_BASE);
|
|
if (space) {
|
|
buf_info.rx_buffer[rx_put++] = c;
|
|
space--;
|
|
}
|
|
if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO)
|
|
rx_put = 0;
|
|
if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
|
|
/* Stop flow by setting RTS inactive */
|
|
out8 (ACTING_UART0_BASE + UART_MCR,
|
|
in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
|
|
}
|
|
}
|
|
buf_info.rx_put = rx_put;
|
|
}
|
|
|
|
void serial_buffered_init (void)
|
|
{
|
|
serial_puts ("Switching to interrupt driven serial input mode.\n");
|
|
buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO);
|
|
buf_info.rx_put = 0;
|
|
buf_info.rx_get = 0;
|
|
|
|
if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
|
|
serial_puts ("Check CTS signal present on serial port: OK.\n");
|
|
} else {
|
|
serial_puts ("WARNING: CTS signal not present on serial port.\n");
|
|
}
|
|
|
|
irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
|
|
serial_isr /*interrupt_handler_t *handler */ ,
|
|
(void *) &buf_info /*void *arg */ );
|
|
|
|
/* Enable "RX Data Available" Interrupt on UART */
|
|
/* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
|
|
out8 (ACTING_UART0_BASE + UART_IER, 0x01);
|
|
/* Set DTR active */
|
|
out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
|
|
/* Start flow by setting RTS active */
|
|
out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
|
|
/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
|
|
out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
|
|
}
|
|
|
|
void serial_buffered_putc (const char c)
|
|
{
|
|
/* Wait for CTS */
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
|
|
WATCHDOG_RESET ();
|
|
#else
|
|
while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
|
|
#endif
|
|
serial_putc (c);
|
|
}
|
|
|
|
void serial_buffered_puts (const char *s)
|
|
{
|
|
serial_puts (s);
|
|
}
|
|
|
|
int serial_buffered_getc (void)
|
|
{
|
|
int space;
|
|
int c;
|
|
int rx_get = buf_info.rx_get;
|
|
int rx_put;
|
|
|
|
#if defined(CONFIG_HW_WATCHDOG)
|
|
while (rx_get == buf_info.rx_put)
|
|
WATCHDOG_RESET ();
|
|
#else
|
|
while (rx_get == buf_info.rx_put);
|
|
#endif
|
|
c = buf_info.rx_buffer[rx_get++];
|
|
if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO)
|
|
rx_get = 0;
|
|
buf_info.rx_get = rx_get;
|
|
|
|
rx_put = buf_info.rx_put;
|
|
if (rx_get <= rx_put) {
|
|
space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get);
|
|
} else {
|
|
space = rx_get - rx_put;
|
|
}
|
|
if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
|
|
/* Start flow by setting RTS active */
|
|
out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
|
|
}
|
|
|
|
return c;
|
|
}
|
|
|
|
int serial_buffered_tstc (void)
|
|
{
|
|
return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0;
|
|
}
|
|
|
|
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
|
|
|
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
|
/*
|
|
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
|
|
number 0 or number 1
|
|
- if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 :
|
|
configuration has been already done
|
|
- if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 :
|
|
configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE
|
|
*/
|
|
#if (CONFIG_KGDB_SER_INDEX & 2)
|
|
void kgdb_serial_init (void)
|
|
{
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
volatile char val;
|
|
unsigned short br_reg;
|
|
|
|
get_clocks ();
|
|
br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) +
|
|
5) / 10;
|
|
/*
|
|
* Init onboard 16550 UART
|
|
*/
|
|
out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
|
out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
|
|
out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
|
|
out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
|
|
out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
|
|
out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
|
|
val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
|
|
val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
|
|
out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
|
|
out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
|
}
|
|
|
|
void putDebugChar (const char c)
|
|
{
|
|
if (c == '\n')
|
|
serial_putc ('\r');
|
|
|
|
out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
|
|
|
|
/* check THRE bit, wait for transfer done */
|
|
while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
|
}
|
|
|
|
void putDebugStr (const char *s)
|
|
{
|
|
while (*s) {
|
|
serial_putc (*s++);
|
|
}
|
|
}
|
|
|
|
int getDebugChar (void)
|
|
{
|
|
unsigned char status = 0;
|
|
|
|
while (1) {
|
|
status = in8 (ACTING_UART1_BASE + UART_LSR);
|
|
if ((status & asyncLSRDataReady1) != 0x0) {
|
|
break;
|
|
}
|
|
if ((status & ( asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1 )) != 0) {
|
|
out8 (ACTING_UART1_BASE + UART_LSR,
|
|
asyncLSRFramingError1 |
|
|
asyncLSROverrunError1 |
|
|
asyncLSRParityError1 |
|
|
asyncLSRBreakInterrupt1);
|
|
}
|
|
}
|
|
return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
|
|
}
|
|
|
|
void kgdb_interruptible (int yes)
|
|
{
|
|
return;
|
|
}
|
|
|
|
#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */
|
|
|
|
void kgdb_serial_init (void)
|
|
{
|
|
serial_printf ("[on serial] ");
|
|
}
|
|
|
|
void putDebugChar (int c)
|
|
{
|
|
serial_putc (c);
|
|
}
|
|
|
|
void putDebugStr (const char *str)
|
|
{
|
|
serial_puts (str);
|
|
}
|
|
|
|
int getDebugChar (void)
|
|
{
|
|
return serial_getc ();
|
|
}
|
|
|
|
void kgdb_interruptible (int yes)
|
|
{
|
|
return;
|
|
}
|
|
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
|
|
#endif /* CFG_CMD_KGDB */
|
|
|
|
|
|
#if defined(CONFIG_SERIAL_MULTI)
|
|
int serial0_init(void)
|
|
{
|
|
return (serial_init_dev(UART0_BASE));
|
|
}
|
|
|
|
int serial1_init(void)
|
|
{
|
|
return (serial_init_dev(UART1_BASE));
|
|
}
|
|
void serial0_setbrg (void)
|
|
{
|
|
serial_setbrg_dev(UART0_BASE);
|
|
}
|
|
void serial1_setbrg (void)
|
|
{
|
|
serial_setbrg_dev(UART1_BASE);
|
|
}
|
|
|
|
void serial0_putc(const char c)
|
|
{
|
|
serial_putc_dev(UART0_BASE,c);
|
|
}
|
|
|
|
void serial1_putc(const char c)
|
|
{
|
|
serial_putc_dev(UART1_BASE, c);
|
|
}
|
|
void serial0_puts(const char *s)
|
|
{
|
|
serial_puts_dev(UART0_BASE, s);
|
|
}
|
|
|
|
void serial1_puts(const char *s)
|
|
{
|
|
serial_puts_dev(UART1_BASE, s);
|
|
}
|
|
|
|
int serial0_getc(void)
|
|
{
|
|
return(serial_getc_dev(UART0_BASE));
|
|
}
|
|
|
|
int serial1_getc(void)
|
|
{
|
|
return(serial_getc_dev(UART1_BASE));
|
|
}
|
|
int serial0_tstc(void)
|
|
{
|
|
return (serial_tstc_dev(UART0_BASE));
|
|
}
|
|
|
|
int serial1_tstc(void)
|
|
{
|
|
return (serial_tstc_dev(UART1_BASE));
|
|
}
|
|
|
|
struct serial_device serial0_device =
|
|
{
|
|
"serial0",
|
|
"UART0",
|
|
serial0_init,
|
|
serial0_setbrg,
|
|
serial0_getc,
|
|
serial0_tstc,
|
|
serial0_putc,
|
|
serial0_puts,
|
|
};
|
|
|
|
struct serial_device serial1_device =
|
|
{
|
|
"serial1",
|
|
"UART1",
|
|
serial1_init,
|
|
serial1_setbrg,
|
|
serial1_getc,
|
|
serial1_tstc,
|
|
serial1_putc,
|
|
serial1_puts,
|
|
};
|
|
#endif /* CONFIG_SERIAL_MULTI */
|
|
|
|
#endif /* CONFIG_405GP || CONFIG_405CR */
|