mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-02-16 14:08:45 +00:00
* Patch by Leif Lindholm, 23 Sep 2004:
add support for the AMD db1550 board * Patch by Travis Sawyer, 15 Sep 2004: Add CONFIG_SERIAL_MULTI support for ppc4xx, update README.serial_multi
This commit is contained in:
wdenk
parent
6310eb9da7
commit
ff36fd8591
14 changed files with 608 additions and 54 deletions
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@ -2,6 +2,13 @@
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Changes for U-Boot 1.1.3:
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======================================================================
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* Patch by Leif Lindholm, 23 Sep 2004:
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add support for the AMD db1550 board
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* Patch by Travis Sawyer, 15 Sep 2004:
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Add CONFIG_SERIAL_MULTI support for ppc4xx,
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update README.serial_multi
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* Patches by David Snowdon, 07 Sep 2004:
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- add u-boot.hex target in the top level Makefile
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- add support for the UNSW/NICTA PLEB 2 board (pleb2)
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4
CREDITS
4
CREDITS
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@ -253,6 +253,10 @@ E: team@leox.org
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D: Support for LEOX boards, DS164x RTC
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W: http://www.leox.org
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N: Leif Lindholm
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E: leif.lindholm@i3micro.com
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D: Support for AMD dbau1550 board.
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N: Stephan Linz
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E: linz@li-pro.net
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D: Support for Nios Stratix Development Kit (DK-1S10)
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4
MAKEALL
4
MAKEALL
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@ -180,9 +180,9 @@ LIST_mips4kc="incaip"
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LIST_mips5kc="purple"
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LIST_au1x00="dbau1000 dbau1100 dbau1500"
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LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el"
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LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1x00}"
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LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
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#########################################################################
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## i386 Systems
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10
Makefile
10
Makefile
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@ -1467,6 +1467,16 @@ dbau1500_config : unconfig
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@echo "#define CONFIG_DBAU1500 1" >>include/config.h
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@./mkconfig -a dbau1x00 mips mips dbau1x00
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dbau1550_config : unconfig
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@ >include/config.h
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@echo "#define CONFIG_DBAU1550 1" >>include/config.h
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@./mkconfig -a dbau1x00 mips mips dbau1x00
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dbau1550_el_config : unconfig
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@ >include/config.h
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@echo "#define CONFIG_DBAU1550 1" >>include/config.h
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@./mkconfig -a dbau1x00 mips mips dbau1x00 "" little
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#########################################################################
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## MIPS64 5Kc
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#########################################################################
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@ -30,7 +30,7 @@ long int initdram(int board_type)
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{
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/* Sdram is setup by assembler code */
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/* If memory could be changed, we should return the true value here */
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return 64*1024*1024;
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return MEM_SIZE*1024*1024;
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}
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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@ -42,8 +42,8 @@ void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
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int checkboard (void)
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{
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u16 status;
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volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10);
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volatile u32 *phy = (u32*)(DB1000_BCSR_ADDR+0xC);
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volatile u32 *pcmcia_bcsr = (u32*)(DB1XX0_BCSR_ADDR+0x10);
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volatile u32 *phy = (u32*)(DB1XX0_BCSR_ADDR+0xC);
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volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
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u32 proc_id;
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@ -67,6 +67,11 @@ int checkboard (void)
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printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
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(proc_id >> 8) & 0xFF, proc_id & 0xFF);
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break;
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case 3:
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puts ("Board: DbAu1550\n");
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printf ("CPU: Au1550, id: 0x%02x, rev: 0x%02x\n",
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(proc_id >> 8) & 0xFF, proc_id & 0xFF);
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break;
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default:
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printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
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}
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@ -9,7 +9,8 @@
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#define AU1500_SYS_ADDR 0xB1900000
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#define sys_endian 0x0038
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#define CP0_Config0 $16
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#define MEM_1MS ((396000000/1000000) * 1000)
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#define CPU_SCALE ((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
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#define MEM_1MS ((CFG_MHZ) * 1000)
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.text
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.set noreorder
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@ -23,6 +24,19 @@ memsetup:
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* Switch S1.1 Off(bit7 reads 1) is Little Endian
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* Switch S1.1 On (bit7 reads 0) is Big Endian
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*/
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#ifdef CONFIG_DBAU1550
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li t0, MEM_STCFG2
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li t1, 0x00000040
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sw t1, 0(t0)
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li t0, MEM_STTIME2
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li t1, 0x22080a20
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sw t1, 0(t0)
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li t0, MEM_STADDR2
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li t1, 0x10c03f00
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sw t1, 0(t0)
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#else
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li t0, MEM_STCFG1
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li t1, 0x00000080
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sw t1, 0(t0)
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@ -34,9 +48,10 @@ memsetup:
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li t0, MEM_STADDR1
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li t1, 0x10c03f00
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sw t1, 0(t0)
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#endif
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li t0, 0xAE000008
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lw t1,0(t0)
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li t0, DB1XX0_BCSR_ADDR
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lw t1,8(t0)
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andi t1,t1,0x80
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beq zero,t1,big_endian
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nop
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@ -98,10 +113,82 @@ big_endian:
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mtc0 zero, CP0_WIRED
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nop
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#ifdef CONFIG_DBAU1550
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/* No workaround if running from ram */
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lui t0, 0xffc0
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lui t3, 0xbfc0
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and t1, ra, t0
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bne t1, t3, noCacheJump
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nop
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/*** From AMD YAMON ***/
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/*
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* Step 8) Initialize the caches
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*/
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li t0, (16*1024)
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li t1, 32
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li t2, 0x80000000
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addu t3, t0, t2
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cacheloop:
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cache 0, 0(t2)
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cache 1, 0(t2)
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addu t2, t1
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bne t2, t3, cacheloop
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nop
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/* Save return address */
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move t3, ra
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/* Run from cacheable space now */
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bal cachehere
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nop
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cachehere:
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li t1, ~0x20000000 /* convert to KSEG0 */
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and t0, ra, t1
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addi t0, 5*4 /* 5 insns beyond cachehere */
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jr t0
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nop
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/* Restore return address */
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move ra, t3
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/*
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* Step 9) Initialize the TLB
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*/
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li t0, 0 # index value
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li t1, 0x00000000 # entryhi value
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li t2, 32 # 32 entries
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tlbloop:
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/* Probe TLB for matching EntryHi */
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mtc0 t1, CP0_ENTRYHI
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tlbp
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nop
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/* Examine Index[P], 1=no matching entry */
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mfc0 t3, CP0_INDEX
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li t4, 0x80000000
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and t3, t4, t3
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addiu t1, t1, 1 # increment t1 (asid)
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beq zero, t3, tlbloop
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nop
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/* Initialize the TLB entry */
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mtc0 t0, CP0_INDEX
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mtc0 zero, CP0_ENTRYLO0
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mtc0 zero, CP0_ENTRYLO1
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mtc0 zero, CP0_PAGEMASK
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tlbwi
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/* Do it again */
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addiu t0, t0, 1
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bne t0, t2, tlbloop
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nop
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/* First setup pll:s to make serial work ok */
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/* We have a 12 MHz crystal */
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li t0, SYS_CPUPLL
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li t1, 0x21 /* 396 MHz */
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li t1, CPU_SCALE /* CPU clock */
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sw t1, 0(t0)
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sync
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nop
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@ -119,19 +206,49 @@ big_endian:
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sync
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/* Static memory controller */
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/* RCE0 - can not change while fetching, do so from icache */
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move t2, ra /* Store return address */
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bal getAddr
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nop
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getAddr:
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move t1, ra
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move ra, t2 /* Move return addess back */
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cache 0x14,0(t1)
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cache 0x14,32(t1)
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/*** /From YAMON ***/
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noCacheJump:
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#endif /* CONFIG_DBAU1550 */
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#ifdef CONFIG_DBAU1550
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li t0, MEM_STTIME0
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li t1, 0x040181D7
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sw t1, 0(t0)
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/* RCE0 AMD MirrorBit Flash (?) */
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li t0, MEM_STCFG0
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li t1, 0x00000003
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sw t1, 0(t0)
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li t0, MEM_STADDR0
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li t1, 0x11803E00
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sw t1, 0(t0)
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#else /* CONFIG_DBAU1550 */
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li t0, MEM_STTIME0
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li t1, 0x00014C0F
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sw t1, 0(t0)
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/* RCE0 AMD 29LV640M MirrorBit Flash */
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li t0, MEM_STCFG0
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li t1, 0x00000013
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sw t1, 0(t0)
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li t0, MEM_STTIME0
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li t1, 0x040181D7
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sw t1, 0(t0)
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li t0, MEM_STADDR0
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li t1, 0x11E03F80
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sw t1, 0(t0)
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#endif /* CONFIG_DBAU1550 */
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/* RCE1 CPLD Board Logic */
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li t0, MEM_STCFG1
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@ -146,7 +263,20 @@ big_endian:
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li t1, 0x10c03f00
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sw t1, 0(t0)
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#ifdef CONFIG_DBAU1550
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/* RCE2 CPLD Board Logic */
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li t0, MEM_STCFG2
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li t1, 0x00000040
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sw t1, 0(t0)
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li t0, MEM_STTIME2
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li t1, 0x22080a20
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sw t1, 0(t0)
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li t0, MEM_STADDR2
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li t1, 0x10c03f00
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sw t1, 0(t0)
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#else
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li t0, MEM_STCFG2
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li t1, 0x00000000
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sw t1, 0(t0)
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@ -158,6 +288,7 @@ big_endian:
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li t0, MEM_STADDR2
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li t1, 0x00000000
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sw t1, 0(t0)
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#endif
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/* RCE3 PCMCIA 250ns */
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li t0, MEM_STCFG3
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@ -281,6 +412,99 @@ big_endian:
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bne t1, zero, 1b
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nop
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#ifdef CONFIG_DBAU1550
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/* SDCS 0,1,2 DDR SDRAM */
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li t0, MEM_SDMODE0
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li t1, 0x04276221
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sw t1, 0(t0)
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li t0, MEM_SDMODE1
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li t1, 0x04276221
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sw t1, 0(t0)
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li t0, MEM_SDMODE2
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li t1, 0x04276221
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sw t1, 0(t0)
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li t0, MEM_SDADDR0
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li t1, 0xe21003f0
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sw t1, 0(t0)
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li t0, MEM_SDADDR1
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li t1, 0xe21043f0
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sw t1, 0(t0)
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li t0, MEM_SDADDR2
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li t1, 0xe21083f0
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sw t1, 0(t0)
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sync
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li t0, MEM_SDCONFIGA
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li t1, 0x9030060a /* Program refresh - disabled */
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sw t1, 0(t0)
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sync
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li t0, MEM_SDCONFIGB
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li t1, 0x00028000
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sw t1, 0(t0)
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sync
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li t0, MEM_SDPRECMD /* Precharge all */
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li t1, 0
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD0
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li t1, 0x40000000
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD1
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li t1, 0x40000000
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD2
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li t1, 0x40000000
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD0
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li t1, 0x00000063
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD1
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li t1, 0x00000063
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sw t1, 0(t0)
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sync
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li t0, MEM_SDWRMD2
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li t1, 0x00000063
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sw t1, 0(t0)
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sync
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li t0, MEM_SDPRECMD /* Precharge all */
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sw zero, 0(t0)
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sync
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/* Issue 2 autoref */
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li t0, MEM_SDAUTOREF
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sw zero, 0(t0)
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sync
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li t0, MEM_SDAUTOREF
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sw zero, 0(t0)
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sync
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/* Enable refresh */
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li t0, MEM_SDCONFIGA
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li t1, 0x9830060a /* Program refresh - enabled */
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sw t1, 0(t0)
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sync
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#else /* CONFIG_DBAU1550 */
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/* SDCS 0,1 SDRAM */
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li t0, MEM_SDMODE0
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li t1, 0x005522AA
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@ -339,6 +563,7 @@ big_endian:
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sw t1, 0(t0)
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sync
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#endif /* CONFIG_DBAU1550 */
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/* wait 1mS after setup */
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li t1, MEM_1MS
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1: add t1, -1
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@ -38,6 +38,9 @@ struct serial_device *default_serial_console (void)
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#elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
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|| defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
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return &serial_scc_device;
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#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
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|| defined(CONFIG_405EP)
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return &serial0_device;
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#else
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#error No default console
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#endif
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@ -71,6 +74,12 @@ void serial_initialize (void)
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serial_register (&serial_scc_device);
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#endif
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
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|| defined(CONFIG_405EP)
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serial_register(&serial0_device);
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serial_register(&serial1_device);
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#endif
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serial_assign (default_serial_console ()->name);
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}
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|
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@ -46,10 +46,15 @@
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#define ETH0_BASE AU1500_ETH0_BASE
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#define MAC0_ENABLE AU1500_MAC0_ENABLE
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#else
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#ifdef CONFIG_AU1550
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#define ETH0_BASE AU1550_ETH0_BASE
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#define MAC0_ENABLE AU1550_MAC0_ENABLE
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#else
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#error "No valid cpu set"
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#endif
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#endif
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#endif
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#endif
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#include <common.h>
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#include <malloc.h>
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|
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@ -71,8 +71,8 @@ void serial_setbrg (void)
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volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
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volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
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|
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/* Set baudrate to 115200 */
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*uart_clk = 0x36;
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/* Set baudrate - FIXME for bus speeds != CPU/2 */
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*uart_clk = ((CFG_HZ/(CONFIG_BAUDRATE * 64)));
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|
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/* Set parity, stop bits and word length to 8N1 */
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*uart_lcr = UART_LCR_WLEN8;
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|
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@ -41,13 +41,20 @@
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*/
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/*------------------------------------------------------------------------------- */
|
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|
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/*
|
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* Travis Sawyer 15 September 2004
|
||||
* Added CONFIG_SERIAL_MULTI support
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <commproc.h>
|
||||
#include <asm/processor.h>
|
||||
#include <watchdog.h>
|
||||
#include "vecnum.h"
|
||||
|
||||
#ifdef CONFIG_SERIAL_MULTI
|
||||
#include <serial.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#include <malloc.h>
|
||||
#endif
|
||||
|
|
@ -147,7 +154,6 @@
|
|||
#define asyncXOFFchar 0x13
|
||||
#define asyncXONchar 0x11
|
||||
|
||||
|
||||
/*
|
||||
* Minimal serial functions needed to use one of the SMC ports
|
||||
* as serial console interface.
|
||||
|
|
@ -177,7 +183,6 @@ int serial_init (void)
|
|||
return (0);
|
||||
}
|
||||
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
|
@ -190,7 +195,6 @@ void serial_setbrg (void)
|
|||
out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
|
||||
}
|
||||
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
|
|
@ -208,7 +212,6 @@ void serial_putc (const char c)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
|
|
@ -216,7 +219,6 @@ void serial_puts (const char *s)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
int serial_getc ()
|
||||
{
|
||||
unsigned char status = 0;
|
||||
|
|
@ -240,7 +242,6 @@ int serial_getc ()
|
|||
return (0x000000ff & (int) in8 (asyncRxBufferport1));
|
||||
}
|
||||
|
||||
|
||||
int serial_tstc ()
|
||||
{
|
||||
unsigned char status;
|
||||
|
|
@ -264,7 +265,6 @@ int serial_tstc ()
|
|||
|
||||
#endif /* CONFIG_IOP480 */
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
|
||||
|
||||
|
|
@ -350,7 +350,6 @@ int serial_tstc ()
|
|||
/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */
|
||||
/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */
|
||||
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
/*-----------------------------------------------------------------------------+
|
||||
| Fifo
|
||||
|
|
@ -364,7 +363,6 @@ typedef struct {
|
|||
volatile static serial_buffer_t buf_info;
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK)
|
||||
static void serial_divs (int baudrate, unsigned long *pudiv,
|
||||
unsigned short *pbdiv )
|
||||
|
|
@ -411,14 +409,17 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
|
|||
}
|
||||
#endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK */
|
||||
|
||||
|
||||
/*
|
||||
* Minimal serial functions needed to use one of the SMC ports
|
||||
* as serial console interface.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
int serial_init (void)
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
int serial_init_dev (unsigned long dev_base)
|
||||
#else
|
||||
int serial_init(void)
|
||||
#endif
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -431,8 +432,18 @@ int serial_init (void)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_440_GX)
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
if (UART0_BASE == dev_base) {
|
||||
mfsdr(UART0_SDR,reg);
|
||||
reg &= ~CR0_MASK;
|
||||
} else {
|
||||
mfsdr(UART1_SDR,reg);
|
||||
reg &= ~CR0_MASK;
|
||||
}
|
||||
#else
|
||||
mfsdr(UART0_SDR,reg);
|
||||
reg &= ~CR0_MASK;
|
||||
#endif
|
||||
#else
|
||||
reg = mfdcr(cntrl0) & ~CR0_MASK;
|
||||
#endif /* CONFIG_440_GX */
|
||||
|
|
@ -451,11 +462,32 @@ int serial_init (void)
|
|||
|
||||
#if defined(CONFIG_440_GX)
|
||||
reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
if (UART0_BASE == dev_base) {
|
||||
mtsdr (UART0_SDR,reg);
|
||||
} else {
|
||||
mtsdr (UART1_SDR,reg);
|
||||
}
|
||||
#else
|
||||
mtsdr (UART0_SDR,reg);
|
||||
#endif
|
||||
#else
|
||||
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
|
||||
mtdcr (cntrl0, reg);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
||||
out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
|
||||
out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
|
||||
val = in8 (dev_base + UART_LSR); /* clear line status */
|
||||
val = in8 (dev_base + UART_RBR); /* read receive buffer */
|
||||
out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
|
||||
out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
#else
|
||||
out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
||||
|
|
@ -466,13 +498,17 @@ int serial_init (void)
|
|||
val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
|
||||
out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
|
||||
out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
|
||||
#endif
|
||||
return (0);
|
||||
}
|
||||
|
||||
#else /* !defined(CONFIG_440) */
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
int serial_init_dev (unsigned long dev_base)
|
||||
#else
|
||||
int serial_init (void)
|
||||
#endif
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -517,6 +553,18 @@ int serial_init (void)
|
|||
tmp = gd->baudrate * udiv * 16;
|
||||
bdiv = (clk + tmp / 2) / tmp;
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
||||
out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
out8 (dev_base + UART_FCR, 0x00); /* disable FIFO */
|
||||
out8 (dev_base + UART_MCR, 0x00); /* no modem control DTR RTS */
|
||||
val = in8 (dev_base + UART_LSR); /* clear line status */
|
||||
val = in8 (dev_base + UART_RBR); /* read receive buffer */
|
||||
out8 (dev_base + UART_SCR, 0x00); /* set scratchpad */
|
||||
out8 (dev_base + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
#else
|
||||
out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
||||
|
|
@ -527,13 +575,17 @@ int serial_init (void)
|
|||
val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
|
||||
out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
|
||||
out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
|
||||
#endif
|
||||
return (0);
|
||||
}
|
||||
|
||||
#endif /* if defined(CONFIG_440) */
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
void serial_setbrg_dev (unsigned long dev_base)
|
||||
#else
|
||||
void serial_setbrg (void)
|
||||
#endif
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -556,39 +608,71 @@ void serial_setbrg (void)
|
|||
tmp = gd->baudrate * udiv * 16;
|
||||
bdiv = (clk + tmp / 2) / tmp;
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
out8 (dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8 (dev_base + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
||||
out8 (dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
#else
|
||||
out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
|
||||
out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
void serial_putc_dev (unsigned long dev_base, const char c)
|
||||
#else
|
||||
void serial_putc (const char c)
|
||||
#endif
|
||||
{
|
||||
int i;
|
||||
|
||||
if (c == '\n')
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
serial_putc_dev (dev_base, '\r');
|
||||
#else
|
||||
serial_putc ('\r');
|
||||
#endif
|
||||
|
||||
/* check THRE bit, wait for transmiter available */
|
||||
for (i = 1; i < 3500; i++) {
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
if ((in8 (dev_base + UART_LSR) & 0x20) == 0x20)
|
||||
#else
|
||||
if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
|
||||
#endif
|
||||
break;
|
||||
udelay (100);
|
||||
}
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
out8 (dev_base + UART_THR, c); /* put character out */
|
||||
#else
|
||||
out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
void serial_puts_dev (unsigned long dev_base, const char *s)
|
||||
#else
|
||||
void serial_puts (const char *s)
|
||||
#endif
|
||||
{
|
||||
while (*s) {
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
serial_putc_dev (dev_base, *s++);
|
||||
#else
|
||||
serial_putc (*s++);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int serial_getc ()
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
int serial_getc_dev (unsigned long dev_base)
|
||||
#else
|
||||
int serial_getc (void)
|
||||
#endif
|
||||
{
|
||||
unsigned char status = 0;
|
||||
|
||||
|
|
@ -596,7 +680,11 @@ int serial_getc ()
|
|||
#if defined(CONFIG_HW_WATCHDOG)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
#endif /* CONFIG_HW_WATCHDOG */
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
status = in8 (dev_base + UART_LSR);
|
||||
#else
|
||||
status = in8 (ACTING_UART0_BASE + UART_LSR);
|
||||
#endif
|
||||
if ((status & asyncLSRDataReady1) != 0x0) {
|
||||
break;
|
||||
}
|
||||
|
|
@ -604,22 +692,37 @@ int serial_getc ()
|
|||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
out8 (dev_base + UART_LSR,
|
||||
#else
|
||||
out8 (ACTING_UART0_BASE + UART_LSR,
|
||||
#endif
|
||||
asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1);
|
||||
}
|
||||
}
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
return (0x000000ff & (int) in8 (dev_base));
|
||||
#else
|
||||
return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
int serial_tstc ()
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
int serial_tstc_dev (unsigned long dev_base)
|
||||
#else
|
||||
int serial_tstc (void)
|
||||
#endif
|
||||
{
|
||||
unsigned char status;
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
status = in8 (dev_base + UART_LSR);
|
||||
#else
|
||||
status = in8 (ACTING_UART0_BASE + UART_LSR);
|
||||
#endif
|
||||
if ((status & asyncLSRDataReady1) != 0x0) {
|
||||
return (1);
|
||||
}
|
||||
|
|
@ -627,7 +730,11 @@ int serial_tstc ()
|
|||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
asyncLSRBreakInterrupt1 )) != 0) {
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
out8 (dev_base + UART_LSR,
|
||||
#else
|
||||
out8 (ACTING_UART0_BASE + UART_LSR,
|
||||
#endif
|
||||
asyncLSRFramingError1 |
|
||||
asyncLSROverrunError1 |
|
||||
asyncLSRParityError1 |
|
||||
|
|
@ -636,7 +743,6 @@ int serial_tstc ()
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
|
||||
void serial_isr (void *arg)
|
||||
|
|
@ -651,8 +757,8 @@ void serial_isr (void *arg)
|
|||
} else {
|
||||
space = rx_get - rx_put;
|
||||
}
|
||||
while (serial_tstc ()) {
|
||||
c = serial_getc ();
|
||||
while (serial_tstc_dev (ACTING_UART0_BASE)) {
|
||||
c = serial_getc_dev (ACTING_UART0_BASE);
|
||||
if (space) {
|
||||
buf_info.rx_buffer[rx_put++] = c;
|
||||
space--;
|
||||
|
|
@ -752,7 +858,6 @@ int serial_buffered_tstc (void)
|
|||
|
||||
#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */
|
||||
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
/*
|
||||
AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port
|
||||
|
|
@ -788,7 +893,6 @@ void kgdb_serial_init (void)
|
|||
out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
|
||||
}
|
||||
|
||||
|
||||
void putDebugChar (const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
|
|
@ -800,7 +904,6 @@ void putDebugChar (const char c)
|
|||
while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
|
||||
}
|
||||
|
||||
|
||||
void putDebugStr (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
|
|
@ -808,7 +911,6 @@ void putDebugStr (const char *s)
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
int getDebugChar (void)
|
||||
{
|
||||
unsigned char status = 0;
|
||||
|
|
@ -832,7 +934,6 @@ int getDebugChar (void)
|
|||
return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
|
||||
}
|
||||
|
||||
|
||||
void kgdb_interruptible (int yes)
|
||||
{
|
||||
return;
|
||||
|
|
@ -867,4 +968,87 @@ void kgdb_interruptible (int yes)
|
|||
#endif /* (CONFIG_KGDB_SER_INDEX & 2) */
|
||||
#endif /* CFG_CMD_KGDB */
|
||||
|
||||
|
||||
#if defined(CONFIG_SERIAL_MULTI)
|
||||
int serial0_init(void)
|
||||
{
|
||||
return (serial_init_dev(UART0_BASE));
|
||||
}
|
||||
|
||||
int serial1_init(void)
|
||||
{
|
||||
return (serial_init_dev(UART1_BASE));
|
||||
}
|
||||
void serial0_setbrg (void)
|
||||
{
|
||||
serial_setbrg_dev(UART0_BASE);
|
||||
}
|
||||
void serial1_setbrg (void)
|
||||
{
|
||||
serial_setbrg_dev(UART1_BASE);
|
||||
}
|
||||
|
||||
void serial0_putc(const char c)
|
||||
{
|
||||
serial_putc_dev(UART0_BASE,c);
|
||||
}
|
||||
|
||||
void serial1_putc(const char c)
|
||||
{
|
||||
serial_putc_dev(UART1_BASE, c);
|
||||
}
|
||||
void serial0_puts(const char *s)
|
||||
{
|
||||
serial_puts_dev(UART0_BASE, s);
|
||||
}
|
||||
|
||||
void serial1_puts(const char *s)
|
||||
{
|
||||
serial_puts_dev(UART1_BASE, s);
|
||||
}
|
||||
|
||||
int serial0_getc(void)
|
||||
{
|
||||
return(serial_getc_dev(UART0_BASE));
|
||||
}
|
||||
|
||||
int serial1_getc(void)
|
||||
{
|
||||
return(serial_getc_dev(UART1_BASE));
|
||||
}
|
||||
int serial0_tstc(void)
|
||||
{
|
||||
return (serial_tstc_dev(UART0_BASE));
|
||||
}
|
||||
|
||||
int serial1_tstc(void)
|
||||
{
|
||||
return (serial_tstc_dev(UART1_BASE));
|
||||
}
|
||||
|
||||
struct serial_device serial0_device =
|
||||
{
|
||||
"serial0",
|
||||
"UART0",
|
||||
serial0_init,
|
||||
serial0_setbrg,
|
||||
serial0_getc,
|
||||
serial0_tstc,
|
||||
serial0_putc,
|
||||
serial0_puts,
|
||||
};
|
||||
|
||||
struct serial_device serial1_device =
|
||||
{
|
||||
"serial1",
|
||||
"UART1",
|
||||
serial1_init,
|
||||
serial1_setbrg,
|
||||
serial1_getc,
|
||||
serial1_tstc,
|
||||
serial1_putc,
|
||||
serial1_puts,
|
||||
};
|
||||
#endif /* CONFIG_SERIAL_MULTI */
|
||||
|
||||
#endif /* CONFIG_405GP || CONFIG_405CR */
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@ The support for multiple serial interfaces as implemented is mainly
|
|||
intended to allow for modem dial-in / dial-out while still being able
|
||||
to use a serial console on a (different) serial port.
|
||||
|
||||
MPC8XX Specific
|
||||
===============
|
||||
At the moment, the ports must be split on a SMC and a SCC port on a
|
||||
8xx processor; other configurations are not (yet) supported.
|
||||
|
||||
|
|
@ -35,3 +37,18 @@ just after switching the console:
|
|||
After that press 'enter' at the SCC console. Note that baudrates <38400
|
||||
are not allowed on LWMON with watchdog enabled (see CFG_BAUDRATE_TABLE in
|
||||
include/configs/lwmon.h).
|
||||
|
||||
|
||||
PPC4XX Specific
|
||||
===============
|
||||
*) The default console is UART0
|
||||
|
||||
*) The console can be switched to UART1 by any of the following commands:
|
||||
setenv stdout serial1
|
||||
setenv stderr serial1
|
||||
setenv stdin serial1
|
||||
|
||||
*) The console can be switched to UART0 by any of the following commands:
|
||||
setenv stdout serial0
|
||||
setenv stderr serial0
|
||||
setenv stdin serial0
|
||||
|
|
|
|||
|
|
@ -132,6 +132,27 @@ static __inline__ int au_ffs(int x)
|
|||
#define CP0_DEBUG $23
|
||||
|
||||
/* SDRAM Controller */
|
||||
#ifdef CONFIG_AU1550
|
||||
|
||||
#define MEM_SDMODE0 0xB4000800
|
||||
#define MEM_SDMODE1 0xB4000808
|
||||
#define MEM_SDMODE2 0xB4000810
|
||||
|
||||
#define MEM_SDADDR0 0xB4000820
|
||||
#define MEM_SDADDR1 0xB4000828
|
||||
#define MEM_SDADDR2 0xB4000830
|
||||
|
||||
#define MEM_SDCONFIGA 0xB4000840
|
||||
#define MEM_SDCONFIGB 0xB4000848
|
||||
#define MEM_SDPRECMD 0xB40008c0
|
||||
#define MEM_SDAUTOREF 0xB40008c8
|
||||
|
||||
#define MEM_SDWRMD0 0xB4000880
|
||||
#define MEM_SDWRMD1 0xB4000888
|
||||
#define MEM_SDWRMD2 0xB4000890
|
||||
|
||||
#else /* CONFIG_AU1550 */
|
||||
|
||||
#define MEM_SDMODE0 0xB4000000
|
||||
#define MEM_SDMODE1 0xB4000004
|
||||
#define MEM_SDMODE2 0xB4000008
|
||||
|
|
@ -148,6 +169,8 @@ static __inline__ int au_ffs(int x)
|
|||
#define MEM_SDWRMD1 0xB4000028
|
||||
#define MEM_SDWRMD2 0xB400002C
|
||||
|
||||
#endif /* CONFIG_AU1550 */
|
||||
|
||||
#define MEM_SDSLEEP 0xB4000030
|
||||
#define MEM_SDSMCKE 0xB4000034
|
||||
|
||||
|
|
@ -474,6 +497,8 @@ static __inline__ int au_ffs(int x)
|
|||
#define AU1500_ETH0_BASE 0xB1500000
|
||||
#define AU1500_ETH1_BASE 0xB1510000
|
||||
#define AU1100_ETH0_BASE 0xB0500000
|
||||
#define AU1550_ETH0_BASE 0xB0500000
|
||||
#define AU1550_ETH1_BASE 0xB0510000
|
||||
|
||||
/* 4 byte offsets from AU1000_ETH_BASE */
|
||||
#define MAC_CONTROL 0x0
|
||||
|
|
@ -523,6 +548,8 @@ static __inline__ int au_ffs(int x)
|
|||
#define AU1500_MAC0_ENABLE 0xB1520000
|
||||
#define AU1500_MAC1_ENABLE 0xB1520004
|
||||
#define AU1100_MAC0_ENABLE 0xB0520000
|
||||
#define AU1550_MAC0_ENABLE 0xB0520000
|
||||
#define AU1550_MAC1_ENABLE 0xB0520004
|
||||
|
||||
#define MAC_EN_CLOCK_ENABLE (1<<0)
|
||||
#define MAC_EN_RESET0 (1<<1)
|
||||
|
|
@ -979,6 +1006,15 @@ static __inline__ int au_ffs(int x)
|
|||
#define AC97C_RS (1<<1)
|
||||
#define AC97C_CE (1<<0)
|
||||
|
||||
#define DB1000_BCSR_ADDR 0xAE000000
|
||||
#define DB1550_BCSR_ADDR 0xAF000000
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
#define DB1XX0_BCSR_ADDR DB1550_BCSR_ADDR
|
||||
#else
|
||||
#define DB1XX0_BCSR_ADDR DB1000_BCSR_ADDR
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SOC_AU1500
|
||||
/* Au1500 PCI Controller */
|
||||
#define Au1500_CFG_BASE 0xB4005000 /* virtual, kseg0 addr */
|
||||
|
|
|
|||
|
|
@ -42,10 +42,15 @@
|
|||
#ifdef CONFIG_DBAU1500
|
||||
#define CONFIG_AU1500 1
|
||||
#else
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* Cabernet */
|
||||
#define CONFIG_AU1550 1
|
||||
#else
|
||||
#error "No valid board set"
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
|
||||
|
||||
|
|
@ -66,23 +71,34 @@
|
|||
"bootfile=/tftpboot/vmlinux.srec\0" \
|
||||
"load=tftp 80500000 $(u-boot)\0" \
|
||||
""
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
/* Boot from flash by default, revert to bootp */
|
||||
#define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm"
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \
|
||||
CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \
|
||||
CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C))
|
||||
#else /* CONFIG_DBAU1550 */
|
||||
/* Boot from Compact flash partition 2 as default */
|
||||
#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm"
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ELF ) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
|
||||
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \
|
||||
CFG_CMD_BDI | CFG_CMD_BEDBUG))
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \
|
||||
~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \
|
||||
CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \
|
||||
CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG))
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "DbAu1x00 # " /* Monitor Command Prompt */
|
||||
|
||||
#define CFG_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */
|
||||
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args*/
|
||||
|
|
@ -91,7 +107,13 @@
|
|||
|
||||
#define CFG_BOOTPARAMS_LEN 128*1024
|
||||
|
||||
#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */
|
||||
#define CFG_MHZ 396
|
||||
|
||||
#if (CFG_MHZ % 12) != 0
|
||||
#error "Invalid CPU frequency - must be multiple of 12!"
|
||||
#endif
|
||||
|
||||
#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */
|
||||
|
||||
#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
|
||||
|
||||
|
|
@ -103,12 +125,29 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#ifdef CONFIG_DBAU1550
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT (512) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */
|
||||
|
||||
#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2}
|
||||
|
||||
#else /* CONFIG_DBAU1550 */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
|
||||
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
#define CFG_FLASH_CFI 1
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10)
|
||||
|
|
@ -134,8 +173,15 @@
|
|||
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
#ifdef CONFIG_DBAU1550
|
||||
#define MEM_SIZE 192
|
||||
#else
|
||||
#define MEM_SIZE 64
|
||||
#endif
|
||||
|
||||
#define CONFIG_MEMSIZE_IN_BYTES
|
||||
|
||||
#ifndef CONFIG_DBAU1550
|
||||
/*---ATA PCMCIA ------------------------------------*/
|
||||
#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
|
||||
#define CFG_PCMCIA_MEM_ADDR 0x20000000
|
||||
|
|
@ -166,6 +212,7 @@
|
|||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||
#endif /* CONFIG_DBAU1550 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
|
|
@ -174,6 +221,4 @@
|
|||
#define CFG_ICACHE_SIZE 16384
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
|
||||
#define DB1000_BCSR_ADDR 0xAE000000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,13 @@ extern struct serial_device serial_smc_device;
|
|||
extern struct serial_device serial_scc_device;
|
||||
extern struct serial_device * default_serial_console (void);
|
||||
|
||||
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
|
||||
|| defined(CONFIG_405EP)
|
||||
extern struct serial_device serial0_device;
|
||||
extern struct serial_device serial1_device;
|
||||
#endif
|
||||
|
||||
|
||||
extern void serial_initialize(void);
|
||||
extern void serial_devices_init(void);
|
||||
extern int serial_assign(char * name);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue