u-boot/arch/arm/mach-tegra
Stephen Warren bbc1b99e8b ARM: tegra: represent RAM in 1 or 2 banks
Represent all available RAM in either one or two banks. The first bank
describes any RAM below 4GB. The second bank describes any RAM above 4GB.

This split is driven by the following requirements:
- The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
  property for memory below and above the 4GB boundary. The layout of that
  DT property is directly driven by the entries in the U-Boot bank array.
- On systems with RAM beyond a physical address of 4GB, the potential
  existence of a carve-out at the end of RAM below 4GB can only be
  represented using multiple banks, since usable RAM is not contiguous.

While making this change, add a lot more comments re: how and why RAM is
represented in banks, and implement a few more "semantic" functions that
define (and perhaps later detect at run-time) the size of any carve-out.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-08-13 13:06:04 -07:00
..
tegra20 Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. 2015-08-05 15:22:51 -07:00
tegra30 Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. 2015-08-05 15:22:51 -07:00
tegra114 Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. 2015-08-05 15:22:51 -07:00
tegra124 tegra: Correct logic for reading pll_misc in clock_start_pll() 2015-08-13 13:06:04 -07:00
tegra210 tegra: Correct logic for reading pll_misc in clock_start_pll() 2015-08-13 13:06:04 -07:00
ap.c ARM: tegra: move VPR configuration to a later stage 2015-08-06 10:50:03 -07:00
board.c ARM: tegra: query_sdram_size() cleanup 2015-08-13 13:06:04 -07:00
board2.c ARM: tegra: represent RAM in 1 or 2 banks 2015-08-13 13:06:04 -07:00
cache.c ARM: Tegra210: Add support to common Tegra source/config files 2015-07-28 10:30:20 -07:00
clock.c tegra: Correct logic for reading pll_misc in clock_start_pll() 2015-08-13 13:06:04 -07:00
cmd_enterrcm.c ARM: tegra: collect SoC sources into mach-tegra 2015-02-21 08:23:51 -05:00
cpu.c Tegra: PLL: use per-SoC pllinfo table instead of PLL_DIVM/N/P, etc. 2015-08-05 15:22:51 -07:00
cpu.h ARM: Tegra210: Add support to common Tegra source/config files 2015-07-28 10:30:20 -07:00
emc.c ARM: tegra: move NVIDIA common files to arch/arm/mach-tegra 2015-05-13 09:46:19 -07:00
emc.h ARM: tegra: move NVIDIA common files to arch/arm/mach-tegra 2015-05-13 09:46:19 -07:00
gpu.c ARM: tegra: enable GPU DT node when appropriate 2015-08-06 10:50:03 -07:00
Kconfig ARM: Tegra210: Add support to common Tegra source/config files 2015-07-28 10:30:20 -07:00
lowlevel_init.S ARM: Tegra210: Add support to common Tegra source/config files 2015-07-28 10:30:20 -07:00
Makefile ARM: tegra: move VPR configuration to a later stage 2015-08-06 10:50:03 -07:00
pinmux-common.c ARM: tegra: Build warning fixes for 64-bit 2015-07-27 15:54:18 -07:00
powergate.c tegra: Introduce SRAM repair on tegra124 2015-06-09 09:56:14 -07:00
psci.S tegra: Set CNTFRQ for secondary CPUs 2015-05-13 09:24:16 -07:00
pwm.c tegra: pwm: Allow the clock rate to be left as is 2015-05-13 09:24:07 -07:00
spl.c ARM: tegra: collect SoC sources into mach-tegra 2015-02-21 08:23:51 -05:00
sys_info.c ARM: tegra: collect SoC sources into mach-tegra 2015-02-21 08:23:51 -05:00
xusb-padctl.c ARM: tegra: collect SoC sources into mach-tegra 2015-02-21 08:23:51 -05:00