mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
62ce0a02f9
Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().
Fixes: 8b3e97badf ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
127 lines
2.8 KiB
C
127 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Rick Chen <rick@andestech.com>
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*
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* U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
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* The PLIC block holds memory-mapped claim and pending registers
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* associated with software interrupt.
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass-internal.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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#include <cpu.h>
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#include <linux/err.h>
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/* pending register */
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#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
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/* enable register */
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#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
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/* claim register */
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#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
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#define ENABLE_HART_IPI (0x80808080)
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#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
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DECLARE_GLOBAL_DATA_PTR;
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static int enable_ipi(int hart)
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{
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unsigned int en;
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en = ENABLE_HART_IPI >> hart;
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writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
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return 0;
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}
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int riscv_init_ipi(void)
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{
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int ret;
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long *base = syscon_get_first_range(RISCV_SYSCON_PLIC);
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ofnode node;
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struct udevice *dev;
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u32 reg;
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if (IS_ERR(base))
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return PTR_ERR(base);
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gd->arch.plic = base;
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ret = uclass_find_first_device(UCLASS_CPU, &dev);
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if (ret)
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return ret;
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else if (!dev)
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return -ENODEV;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (strcmp(device_type, "cpu"))
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continue;
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/* skip if hart is marked as not available */
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if (!ofnode_is_available(node))
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continue;
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/* read hart ID of CPU */
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ret = ofnode_read_u32(node, "reg", ®);
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if (ret == 0)
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enable_ipi(reg);
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}
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return 0;
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}
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int riscv_send_ipi(int hart)
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{
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unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
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writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
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gd->arch.boot_hart));
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return 0;
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}
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int riscv_clear_ipi(int hart)
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{
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u32 source_id;
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source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
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writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
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*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
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gd->arch.boot_hart));
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*pending = !!(*pending & ipi);
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return 0;
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}
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static const struct udevice_id andes_plic_ids[] = {
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{ .compatible = "riscv,plic1", .data = RISCV_SYSCON_PLIC },
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{ }
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};
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U_BOOT_DRIVER(andes_plic) = {
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.name = "andes_plic",
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.id = UCLASS_SYSCON,
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.of_match = andes_plic_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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