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https://github.com/AsahiLinux/u-boot
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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
82 lines
1.6 KiB
C
82 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Configuration for MediaTek MT8512 SoC
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*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Mingming Lee <mingming.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <wdt.h>
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#include <asm/arch/misc.h>
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#include <asm/armv8/mmu.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt8512-clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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phys_size_t get_effective_memsize(void)
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{
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/* limit stack below tee reserve memory */
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return gd->ram_size - 6 * SZ_1M;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = gd->ram_base;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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return 0;
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}
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void reset_cpu(void)
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{
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struct udevice *watchdog_dev = NULL;
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if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
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if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
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psci_system_reset();
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wdt_expire_now(watchdog_dev, 0);
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}
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int print_cpuinfo(void)
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{
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debug("CPU: MediaTek MT8512\n");
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return 0;
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}
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static struct mm_region mt8512_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt8512_mem_map;
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