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a7fdac7e2a
Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
48 lines
1.2 KiB
Text
48 lines
1.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LS1028A-QDS device tree fragment for RCW x3xx
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*
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* Copyright 2019-2021 NXP Semiconductors
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*/
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/*
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* This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
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* is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
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*
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* We're including the normal .dsti file, not the reworked card .dtsi
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* intentionally. We are using multiplexing of the 4 interfaces on a single
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* lane and the rework doesn't actually disable any port. The rework is in fact
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* needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
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* card.
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*/
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&slot2 {
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#include "fsl-sch-30841.dtsi"
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};
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&mscc_felix {
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status = "okay";
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};
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&mscc_felix_port0 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
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};
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&mscc_felix_port1 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
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};
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&mscc_felix_port2 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
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};
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&mscc_felix_port3 {
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status = "okay";
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phy-mode = "usxgmii";
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phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
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};
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