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arm: dts: ls1028a: define QDS networking protocol combinations

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Includes DT definition for the following serdes protocols using various
PHY cards: 85xx, 13xx, 65xx, 9999, 7777.

Note that the default device tree for QDS now uses 85xx.
Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi
file (the includes at the bottom of the file).

The phy-handle is specified as a path rather than a label because it is
possible to use the #include multiple times (meaning that more than one
PHY riser card of one type is inserted), and therefore, there would be
duplicate labels with the same name.

LBRW means that the board needs lane B rework before using this dtsi.

Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Alex Marginean 2021-01-27 13:00:00 +02:00 committed by Priyanka Jain
parent a94ab561e2
commit a7fdac7e2a
16 changed files with 490 additions and 0 deletions
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20
arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC
* port 0 USXGMII.
*/
&slot1 {
#include "fsl-sch-30842.dtsi"
};
&enetc0 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-30842 cards with AQR112 PHY.
*/
&slot1 {
#include "fsl-sch-30842.dtsi"
};
&enetc0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using a SCH-30841 card with AQR412 10G quad PHY.
*
* Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
* Bottom port is port 0.
* Note that this is only usable for:
* - QDS boards WITHOUT lane B rework,
* - AQR412 card WITHOUT lane A -> lane C rework
*
* The following DTS assumes DIP SW5[1-3] = 000b.
*/
&slot1 {
#include "fsl-sch-30841.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
* Copyright 2019-2021 NXP Semiconductors
*/
&slot1 {
#include "fsl-sch-30841.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

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arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1.
*/
&slot1 {
#include "fsl-sch-24801.dtsi"
};
&enetc0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
* LS1028A QDS boards with lane B rework require two cards for the 4 switch
* ports, QDS boards without the lane B rework only require one card.
*
* Switch ports are routed as follows:
* Port 0 goes to 1st port of VSC8234 quad card in slot 1,
* Port 1:
* - if the QDS has had lane B rework, it is 1st port in slot 2,
* - otherwise it is 2nd port in slot 1.
* Port 2:
* - if DIP SW5[1] = 0 it is 3rd port in slot 1,
* - otherwise it is 1st port in slot 3.
* Port 3:
* - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
* - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
* - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
*
* The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
* SCH-24801 cards are required in slots 1 and 2.
*/
&slot1 {
#include "fsl-sch-24801.dtsi"
};
&slot2 {
#include "fsl-sch-24801.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
*
*/
/*
* This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY.
*
* Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1.
* Top port is port 0.
*
* The following DTS assumes DIP SW5[1-3] = 000b.
*/
&slot1 {
#include "fsl-sch-24801.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
* is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
*
* We're including the normal .dsti file, not the reworked card .dtsi
* intentionally. We are using multiplexing of the 4 interfaces on a single
* lane and the rework doesn't actually disable any port. The rework is in fact
* needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
* card.
*/
&slot2 {
#include "fsl-sch-30841.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "usxgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
* This is only available on LS1028A QDS boards with lane B rework.
*/
&slot2 {
#include "fsl-sch-28021.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port0 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
*/
&slot2 {
#include "fsl-sch-30842.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
*/
&slot3 {
#include "fsl-sch-30842.dtsi"
};
&mscc_felix {
status = "okay";
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};

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&mdio0 {
status = "okay";
};
#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-24801 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards.
* It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
* PHY addresses are 0x1c - 0x1f.
* On the card the first port is the top port (farthest from PEX connector).
*/
phy@1c {
reg = <0x1c>;
};
phy@1d {
reg = <0x1d>;
};
phy@1e {
reg = <0x1e>;
};
phy@1f {
reg = <0x1f>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-28021 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-28021 is a QSGMII add-on card used with various FSL QDS boards.
* It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
* single QSGMII lane.
* PHY addresses are 0x08 - 0x0b.
* On the card the first port is the top port (farthest from PEX connector).
*/
phy@08 {
reg = <0x08>;
};
phy@09 {
reg = <0x09>;
};
phy@0a {
reg = <0x0a>;
};
phy@0b {
reg = <0x0b>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-30841 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
* It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/
phy@00 {
reg = <0x00>;
mdi-reversal = <1>;
smb-addr = <0x25>;
};
phy@01 {
reg = <0x01>;
mdi-reversal = <1>;
smb-addr = <0x26>;
};
phy@02 {
reg = <0x02>;
mdi-reversal = <1>;
smb-addr = <0x27>;
};
phy@03 {
reg = <0x03>;
mdi-reversal = <1>;
smb-addr = <0x28>;
};

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// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Device tree fragment for RCW SCH-30842 card
*
* Copyright 2019-2021 NXP Semiconductors
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
* SGMII-2500, USXGMII, XFI.
* PHY address is 0x02.
*/
phy@02 {
reg = <0x02>;
mdi-reversal = <1>;
smb-addr = <0x25>;
};