mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-30 11:22:09 +00:00
f697471217
Apply a few small fixes for the DTB /memory node parsing from NVIDIA's downstream U-Boot: - Allow arbitrary number of DRAM banks. - Correctly calculate the number of DRAM banks. - Clip PCIe memory in the same way as U-Boot CPU memory use. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <asm/arch/tegra.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern unsigned long nvtboot_boot_x0;
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/*
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* A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
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*
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* We assume bank 0 is RAM completely below 4G mostly ignore other banks;
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* assuming they contain RAM above 4G. This is all a fairly safe assumption,
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* since the L4T kernel makes the same assumption, so the bootloader is
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* unlikely to change.
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*
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* This is written to before relocation, and hence cannot be in .bss, since
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* .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
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* forces this into .data and avoids this issue. This also has the nice side-
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* effect of the content being valid after relocation.
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*/
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static struct {
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u64 start;
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u64 size;
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} ram_banks[CONFIG_NR_DRAM_BANKS] = {{1}};
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int dram_init(void)
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{
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unsigned int na, ns;
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const void *nvtboot_blob = (void *)nvtboot_boot_x0;
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int node, len, i;
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const u32 *prop;
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memset(ram_banks, 0, sizeof(ram_banks));
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na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
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ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
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node = fdt_path_offset(nvtboot_blob, "/memory");
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if (node < 0) {
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pr_err("Can't find /memory node in nvtboot DTB");
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hang();
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}
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prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
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if (!prop) {
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pr_err("Can't find /memory/reg property in nvtboot DTB");
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hang();
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}
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/* Calculate the true # of base/size pairs to read */
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len /= 4; /* Convert bytes to number of cells */
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len /= (na + ns); /* Convert cells to number of banks */
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if (len > ARRAY_SIZE(ram_banks))
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len = ARRAY_SIZE(ram_banks);
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gd->ram_size = 0;
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for (i = 0; i < len; i++) {
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ram_banks[i].start = fdt_read_number(prop, na);
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prop += na;
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ram_banks[i].size = fdt_read_number(prop, ns);
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prop += ns;
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gd->ram_size += ram_banks[i].size;
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}
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return 0;
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}
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extern unsigned long nvtboot_boot_x0;
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int dram_init_banksize(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = ram_banks[i].start;
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gd->bd->bi_dram[i].size = ram_banks[i].size;
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}
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#ifdef CONFIG_PCI
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gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
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#endif
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return 0;
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}
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return ram_banks[0].start + ram_banks[0].size;
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}
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