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https://github.com/AsahiLinux/u-boot
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dbd2a382c1
The Zyxel NSA310s board has the network chip Marvell Alaska 88E1318S. Use uclass mvgbe and the compatible driver M88E1310 driver to bring up Ethernet. - Use uclass mvgbe to bring up the network. And remove ad-hoc code. - Remove CONFIG_RESET_PHY_R. - Enable CONFIG_PHY_MARVELL to properly configure the network. - Add phy mode RGMII to kirkwood-nsa310s.dts - Miscellaneous changes: Move constants to .c file and remove header file board/zyxel/nsa310s/nsa310s.h, add support for large USB and SATA HDDs, use BIT macro, add/cleanup comments, and cosmetic changes. Note that this patch is depended on the following patch: https://patchwork.ozlabs.org/project/uboot/patch/20220412201820.10291-1-mibodhi@gmail.com/ Signed-off-by: Tony Dinh <mibodhi@gmail.com>
113 lines
2.1 KiB
C
113 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
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*/
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#include <common.h>
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#include <init.h>
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#include <netdev.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* low GPIO's
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*/
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#define HDD1_GREEN_LED BIT(16)
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#define HDD1_RED_LED BIT(13)
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#define USB_GREEN_LED BIT(15)
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#define USB_POWER BIT(21)
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#define SYS_GREEN_LED BIT(28)
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#define SYS_ORANGE_LED BIT(29)
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#define COPY_GREEN_LED BIT(22)
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#define COPY_RED_LED BIT(23)
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#define PIN_USB_GREEN_LED 15
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#define PIN_USB_POWER 21
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#define NSA310S_OE_LOW (~(0))
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#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
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/*
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* high GPIO's
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*/
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#define HDD2_GREEN_LED BIT(2)
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#define HDD2_POWER BIT(1)
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#define NSA310S_OE_HIGH (~(0))
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#define NSA310S_VAL_HIGH (HDD2_POWER)
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
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NSA310S_OE_LOW, NSA310S_OE_HIGH);
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/* (all LEDs & power off active high) */
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_GPO,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO,
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MPP13_GPIO,
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MPP14_GPIO,
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MPP15_GPIO,
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MPP16_GPIO,
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MPP17_GPIO,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO,
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MPP35_GPIO,
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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int board_eth_init(struct bd_info *bis)
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{
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return cpu_eth_init(bis);
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}
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