u-boot/arch/arm/cpu/armv8/zynqmp
Siva Durga Prasad Paladugu f322ad604e arm64: zynqmp: mp: Correct the R5 release sequence
This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
   A53 can do speculative and may result in ECC failures
   if TCM's are not initialized. So, it is always better
   to disable dcaches before accessing TCM and enable back.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2017-11-28 16:08:56 +01:00
..
clk.c ARM64: zynqmp: Remove get_uart_clk() 2016-07-22 14:04:41 +02:00
cpu.c arm64: zynqmp: remove unnecessary logical constraint 2017-11-28 15:53:07 +01:00
handoff.c ARM64: zynqmp: Generate handoff structure for ATF 2017-01-10 10:22:05 +01:00
Kconfig arm64: zynqmp: Add Kconfig option for adding psu_init to binary 2017-08-02 09:11:52 +02:00
Makefile arm64: zynqmp: Remove slcr with mio status pin detection 2017-11-28 16:08:55 +01:00
mp.c arm64: zynqmp: mp: Correct the R5 release sequence 2017-11-28 16:08:56 +01:00
spl.c arm64: zynqmp: Call psu_init from board_early_init_f 2017-08-02 09:11:52 +02:00